colin
/
Hazard3
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add note on clang-16 to Readme

This commit is contained in:
Luke Wren 2024-08-07 13:15:27 -07:00
parent aa140fb244
commit ddf7fcacdc
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Readme.md
View File

@ -77,7 +77,9 @@ You will need:
* A recent Yosys build to process the Verilog (these instructions were last tested with `b1569de5`) * A recent Yosys build to process the Verilog (these instructions were last tested with `b1569de5`)
* A `riscv32-unknown-elf-` toolchain to build software for the core * A `riscv32-unknown-elf-` toolchain to build software for the core
* A native `clang` to build the simulator * A native `clang-16` to build the simulator
`clang-17` is also known to work fine. `clang-18` does work, but has a serious compile time regression with CXXRTL output, which is why the `tb_cxxrtl` Makefile explicitly selects `clang-16`.
## Yosys ## Yosys