From df0fd536ebcd60d03119258cabcf0315796a1cf0 Mon Sep 17 00:00:00 2001
From: Luke Wren <wren6991@gmail.com>
Date: Mon, 23 May 2022 12:56:37 +0100
Subject: [PATCH] Fix IRQ priority to match the priv spec

---
 hdl/hazard3_csr.v | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/hdl/hazard3_csr.v b/hdl/hazard3_csr.v
index 84cc975..e4f1a23 100644
--- a/hdl/hazard3_csr.v
+++ b/hdl/hazard3_csr.v
@@ -1039,7 +1039,6 @@ wire irq_active = |(mip & mie) && mstatus_mie && !dcsr_step;
 assign wfi_stall_clear = |(mip & mie) || dcsr_step || debug_mode || want_halt_irq_if_no_exception;
 
 wire [6:0] external_irq_num;
-wire [3:0] standard_irq_num;
 assign mlei = external_irq_num;
 
 hazard3_priority_encode #(
@@ -1049,12 +1048,11 @@ hazard3_priority_encode #(
 	.gnt (external_irq_num)
 );
 
-hazard3_priority_encode #(
-	.W_REQ (16)
-) irq_priority (
-	.req (mip[15:0] & mie[15:0]),
-	.gnt (standard_irq_num)
-);
+// Priority order from priv spec: external > software > timer
+wire [3:0] standard_irq_num =
+	mip[11] && mie[11] ? 4'd11 :
+	mip[3]  && mie[3]  ? 4'd3  :
+	mip[7]  && mie[7]  ? 4'd7  : 4'd0;
 
 // ebreak may be treated as a halt-to-debugger or a regular M-mode exception,
 // depending on dcsr.ebreakm.