Add default_nettype none at top of every file, and default_nettype wire at bottom

hdl/arith/hazard3_alu.v

@@ -15,6 +15,8 @@
  *                                                                    *
  *********************************************************************/
 
+`default_nettype none
+
 module hazard3_alu #(
 	parameter W_DATA = 32
 ) (
@@ -113,3 +115,5 @@ end
 `endif
 
 endmodule
+
+`default_nettype wire

hdl/arith/hazard3_mul_fast.v

@@ -15,6 +15,8 @@
  *                                                                    *
  *********************************************************************/
 
+`default_nettype none
+
 module hazard3_mul_fast #(
 	parameter XLEN = 32
 ) (
@@ -73,3 +75,5 @@ always @ (posedge clk or negedge rst_n) begin
 end
 
 endmodule
+
+`default_nettype wire

hdl/arith/hazard3_muldiv_seq.v

@@ -27,6 +27,8 @@
 // The actual multiply/divide hardware is unsigned. We handle signedness at
 // input/output.
 
+`default_nettype none
+
 module hazard3_muldiv_seq #(
 	parameter XLEN = 32,
 	parameter UNROLL = 1,
@@ -232,7 +234,7 @@ assign {result_h, result_l} = accum;
 `else
 
 // Provide arithmetically simpler alternative operations, to speed up formal checks
-always assert(XLEN == 32); // TODO may care about this one day
+always assert(XLEN == 32);
 
 reg [XLEN-1:0] fml_a_saved;
 reg [XLEN-1:0] fml_b_saved;
@@ -293,3 +295,5 @@ end
 `endif
 
 endmodule
+
+`default_nettype wire

hdl/arith/hazard3_priority_encode.v

@@ -18,6 +18,8 @@
 // Really something like this should be in a utility library (or the language!),
 // but Hazard3 is supposed to be self-contained
 
+`default_nettype none
+
 module hazard3_priority_encode #(
 	parameter W_REQ = 16,
 	parameter W_GNT = $clog2(W_REQ) // do not modify
@@ -55,3 +57,5 @@ end
 assign gnt = gnt_accum;
 
 endmodule
+
+`default_nettype wire

hdl/arith/hazard3_shift_barrel.v

@@ -19,6 +19,8 @@
 // using a single log-type barrel shifter. Around 240 LUTs for 32 bits.
 // (7 layers of 32 2-input muxes, some extra LUTs and LUT inputs used for arith)
 
+`default_nettype none
+
 module hazard3_shift_barrel #(
 	parameter W_DATA = 32,
 	parameter W_SHAMT = 5
@@ -65,3 +67,5 @@ end
 `endif
 
 endmodule
+
+`default_nettype wire

hdl/debug/cdc/hazard3_apb_async_bridge.v

@@ -26,6 +26,8 @@
 `define HAZARD3_REG_KEEP_ATTRIBUTE (* keep = 1'b1 *)
 `endif
 
+`default_nettype none
+
 module hazard3_apb_async_bridge #(
     parameter W_ADDR = 8,
     parameter W_DATA = 32,
@@ -203,3 +205,5 @@ assign dst_penable = dst_penable_r;
 assign {dst_paddr, dst_pwdata, dst_pwrite} = dst_paddr_pwdata_pwrite;
 
 endmodule
+
+`default_nettype wire

hdl/debug/cdc/hazard3_reset_sync.v

@@ -26,6 +26,8 @@
 `define HAZARD3_REG_KEEP_ATTRIBUTE (* keep = 1'b1 *)
 `endif
 
+`default_nettype none
+
 module hazard3_reset_sync #(
 	parameter N_STAGES = 2 // Should be >= 2
 ) (
@@ -45,3 +47,5 @@ always @ (posedge clk or negedge rst_n_in)
 assign rst_n_out = delay[N_STAGES-1];
 
 endmodule
+
+`default_nettype wire

hdl/debug/cdc/hazard3_sync_1bit.v

@@ -23,6 +23,8 @@
 `define HAZARD3_REG_KEEP_ATTRIBUTE (* keep = 1'b1 *)
 `endif
 
+`default_nettype none
+
 module hazard3_sync_1bit #(
 	parameter N_STAGES = 2 // Should be >=2
 ) (
@@ -43,3 +45,5 @@ always @ (posedge clk or negedge rst_n)
 assign o = sync_flops[N_STAGES-1];
 
 endmodule
+
+`default_nettype wire

hdl/debug/dm/hazard3_dm.v

@@ -571,3 +571,5 @@ always @ (*) begin
 end
 
 endmodule
+
+`default_nettype wire

hdl/debug/dtm/hazard3_ecp5_jtag_dtm.v

@@ -198,3 +198,5 @@ hazard3_jtag_dtm_core #(
 );
 
 endmodule
+
+`default_nettype wire

hdl/debug/dtm/hazard3_jtag_dtm.v

@@ -214,3 +214,5 @@ hazard3_jtag_dtm_core #(
 );
 
 endmodule
+
+`default_nettype wire

hdl/debug/dtm/hazard3_jtag_dtm_core.v

@@ -23,6 +23,8 @@
 // This core logic can be reused and connected to some other serial transport
 // or, for example, the ECP5 JTAGG primitive (see hazard5_ecp5_jtag_dtm.v)
 
+`default_nettype none
+
 module hazard3_jtag_dtm_core #(
 	parameter DTMCS_IDLE_HINT = 3'd4,
 	parameter W_ADDR = 8,
@@ -190,3 +192,5 @@ always @ (posedge tck or negedge trst_n) begin
 end
 
 endmodule
+
+`default_nettype wire

hdl/debug/dtm/hazard3_uart_dtm.v

@@ -21,6 +21,8 @@
 // This is not suitable for production systems (it's a UART...) but is a
 // simple way to get your FPGA board up and running.
 
+`default_nettype none
+
 module hazard3_uart_dtm #(
     // Expected to run at 1 Mbaud from some fixed reference frequency.
     parameter BAUD_CLKDIV = 12,
@@ -343,3 +345,5 @@ assign paddr = dm_addr;
 assign pwdata = dm_data;
 
 endmodule
+
+`default_nettype wire

hdl/debug/dtm/hazard3_uart_dtm_fifo.v

@@ -17,6 +17,8 @@
 
 // Nothing to see here, just a sync FIFO
 
+`default_nettype none
+
 module hazard3_uart_dtm_fifo #(
 	parameter WIDTH = 8,
 	parameter LOG_DEPTH = 2
@@ -59,3 +61,5 @@ end
 assign rdata = fifo_mem[rptr[LOG_DEPTH-1:0]];
 
 endmodule
+
+`default_nettype wire

hdl/hazard3_core.v

@@ -769,3 +769,5 @@ hazard3_regfile_1w2r #(
 `endif
 
 endmodule
+
+`default_nettype wire

hdl/hazard3_cpu_1port.v

@@ -19,6 +19,8 @@
 // Hazard3 core, and arbitrates its instruction fetch and load/store signals
 // down to a single AHB-Lite master port.
 
+`default_nettype none
+
 module hazard3_cpu_1port #(
 `include "hazard3_config.vh"
 ) (
@@ -239,3 +241,5 @@ assign core_dph_ready_d = ahblm_hready && bus_active_dph_d;
 assign core_dph_err_d = bus_active_dph_d && ahblm_hresp;
 
 endmodule
+
+`default_nettype wire

hdl/hazard3_cpu_2port.v

@@ -19,6 +19,8 @@
 // Hazard3 core, and interfaces its instruction fetch and load/store signals
 // to a pair of AHB-Lite master ports.
 
+`default_nettype none
+
 module hazard3_cpu_2port #(
 `include "hazard3_config.vh"
 ) (
@@ -214,3 +216,5 @@ assign d_hprot = 4'b0010;
 assign d_hmastlock = 1'b0;
 
 endmodule
+
+`default_nettype wire

hdl/hazard3_frontend.v

@@ -391,3 +391,5 @@ assign next_regs_rs2 =
 	next_instr[1:0] == 2'b10 ? next_instr[6:2]   : {2'b01, next_instr[4:2]};
 
 endmodule
+
+`default_nettype wire

hdl/hazard3_instr_decompress.v

@@ -1,3 +1,22 @@
+/******************************************************************************
+ *     DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE         *
+ *                        Version 3, April 2008                               *
+ *                                                                            *
+ *     Copyright (C) 2021 Luke Wren                                           *
+ *                                                                            *
+ *     Everyone is permitted to copy and distribute verbatim or modified      *
+ *     copies of this license document and accompanying software, and         *
+ *     changing either is allowed.                                            *
+ *                                                                            *
+ *       TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION      *
+ *                                                                            *
+ *     0. You just DO WHAT THE FUCK YOU WANT TO.                              *
+ *     1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK.                 *
+ *                                                                            *
+ *****************************************************************************/
+
+`default_nettype none
+
 module hazard3_instr_decompress #(
 	parameter PASSTHROUGH = 0
 ) (
@@ -113,3 +132,5 @@ end
 endgenerate
 
 endmodule
+
+`default_nettype wire

hdl/hazard3_regfile_1w2r.v

@@ -23,6 +23,8 @@
 // This allows BRAM inference on FPGAs with single-read-port BRAMs.
 // (Looking at you iCE40)
 
+`default_nettype none
+
 module hazard3_regfile_1w2r #(
 	parameter FAKE_DUALPORT = 0,
 	parameter RESET_REGS = 0,	// Unsupported for FAKE_DUALPORT
@@ -92,3 +94,5 @@ end
 endgenerate
 
 endmodule
+
+`default_nettype wire

hdl/peri/hazard3_riscv_timer.v

@@ -30,6 +30,8 @@
 // mtimecmp comparison. To pause the timer due to an external event, assert
 // dbg_halt high. To pause from software, write 0 to CTRL.EN.
 
+`default_nettype none
+
 module hazard3_riscv_timer (
 	input  wire               clk,
 	input  wire               rst_n,
@@ -59,6 +61,7 @@ localparam ADDR_MTIMEH    = 8'h0c;
 localparam ADDR_MTIMECMP  = 8'h10;
 localparam ADDR_MTIMECMPH = 8'h14;
 
+wire bus_write = pwrite && psel && penable && pready;
 
 reg ctrl_en;
 always @ (posedge clk or negedge rst_n) begin
@@ -69,7 +72,6 @@ always @ (posedge clk or negedge rst_n) begin
 	end
 end
 
-wire bus_write = pwrite && psel && penable && pready;
 wire tick_and_increment = ctrl_en && !dbg_halt && tick;
 
 // ----------------------------------------------------------------------------
@@ -170,3 +172,5 @@ always @ (*) case (paddr)
 endcase
 
 endmodule
+
+`default_nettype wire