From e44d2e6f9e64cd190f7e1923b181595ef3a8f333 Mon Sep 17 00:00:00 2001
From: Luke Wren <wren6991@gmail.com>
Date: Sun, 3 Jul 2022 23:34:12 +0100
Subject: [PATCH] Add memory sampling to run-debug-tests. Add
 run-smp-debug-tests. Bump riscv-tests to get new SMP target, and a test fix
 for MemorySampleMixed

---
 test/sim/riscv-tests/debug.gtkw             | 56 +++++++++++++++++++++
 test/sim/riscv-tests/riscv-tests            |  2 +-
 test/sim/riscv-tests/run-debug-tests.sh     |  4 +-
 test/sim/riscv-tests/run-smp-debug-tests.sh | 19 +++++++
 4 files changed, 79 insertions(+), 2 deletions(-)
 create mode 100644 test/sim/riscv-tests/debug.gtkw
 create mode 100755 test/sim/riscv-tests/run-smp-debug-tests.sh

diff --git a/test/sim/riscv-tests/debug.gtkw b/test/sim/riscv-tests/debug.gtkw
new file mode 100644
index 0000000..590e60d
--- /dev/null
+++ b/test/sim/riscv-tests/debug.gtkw
@@ -0,0 +1,56 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Sun Jul  3 18:10:08 2022
+[*]
+[dumpfile] "/home/luke/proj/hazard3/test/sim/riscv-tests/riscv-tests/debug/waves.vcd"
+[dumpfile_mtime] "Sun Jul  3 18:08:00 2022"
+[dumpfile_size] 95825843
+[savefile] "/home/luke/proj/hazard3/test/sim/riscv-tests/debug.gtkw"
+[timestart] 519500
+[size] 1920 2096
+[pos] -1 -1
+*-16.000000 771701 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] cpu.
+[treeopen] cpu.core.
+[sst_width] 233
+[signals_width] 182
+[sst_expanded] 1
+[sst_vpaned_height] 665
+@28
+dm.sberror[2:0]
+dm.sbbusy
+dm.sbbusyerror
+@200
+-
+@22
+dm.sbus_addr[31:0]
+@28
+dm.sbaccess[2:0]
+dm.sb_badalign
+dm.sb_want_start_write
+dm.sb_want_start_read
+@200
+-
+-System Bus Request
+@22
+dm.sbus_addr[31:0]
+@28
+dm.sbus_size[1:0]
+dm.sbus_write
+dm.sbus_vld
+dm.sbus_rdy
+dm.sbus_err
+@22
+dm.sbus_wdata[31:0]
+dm.sbus_rdata[31:0]
+@200
+-
+-Core Bus Request
+@28
+cpu.core_aph_req_d
+cpu.core_aph_ready_d
+cpu.core_dph_ready_d
+@201
+-
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/test/sim/riscv-tests/riscv-tests b/test/sim/riscv-tests/riscv-tests
index de4f8d0..0211e0d 160000
--- a/test/sim/riscv-tests/riscv-tests
+++ b/test/sim/riscv-tests/riscv-tests
@@ -1 +1 @@
-Subproject commit de4f8d03fc168a54c23f4254c3724e927daa1828
+Subproject commit 0211e0dacc85d2fa5270e719260f060e21bcc298
diff --git a/test/sim/riscv-tests/run-debug-tests.sh b/test/sim/riscv-tests/run-debug-tests.sh
index d2ef2fa..e0d8a07 100755
--- a/test/sim/riscv-tests/run-debug-tests.sh
+++ b/test/sim/riscv-tests/run-debug-tests.sh
@@ -12,7 +12,7 @@ done
 # Only applicable tests are included
 ./gdbserver.py \
 	--sim_cmd "../../../tb_cxxrtl/tb --port 9824" \
-	--server_cmd riscv-openocd \
+	--server_cmd "riscv-openocd" \
 	--gdb riscv32-unknown-elf-gdb \
 	--gcc riscv32-unknown-elf-gcc \
 	targets/luke/hazard3.py \
@@ -32,6 +32,8 @@ InterruptTest \
 CrashLoop \
 InstantChangePc \
 InstantHaltTest \
+MemorySampleMixed \
+MemorySampleSingle \
 MemTest16 \
 MemTest32 \
 MemTest64 \
diff --git a/test/sim/riscv-tests/run-smp-debug-tests.sh b/test/sim/riscv-tests/run-smp-debug-tests.sh
new file mode 100755
index 0000000..330ef08
--- /dev/null
+++ b/test/sim/riscv-tests/run-smp-debug-tests.sh
@@ -0,0 +1,19 @@
+set -e
+
+make -C ../tb_cxxrtl/ DOTF=tb_multicore.f tb
+# make -C ../tb_cxxrtl/ DOTF=tb_multicore.f clean tb
+cd riscv-tests/debug
+
+# Clean up old logs and test binaries
+rm -rf logs
+for fname in $(find -name "*" -maxdepth 1); do
+	if file ${fname} | grep -q "ELF 32-bit"; then rm ${fname}; fi
+done
+
+# Only applicable tests are included
+./gdbserver.py \
+	--sim_cmd "../../../tb_cxxrtl/tb --port 9824" \
+	--server_cmd riscv-openocd \
+	--gdb riscv32-unknown-elf-gdb \
+	--gcc riscv32-unknown-elf-gcc \
+	targets/luke/hazard3_smp.py