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Minor doc updates

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Luke Wren 2021-07-18 20:45:08 +01:00
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Readme.md
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@ -39,5 +39,6 @@ Hazard3 is still under development.
- `M` memory
- Load/store data phase
- Some complex instructions, particularly multiply and divide
- Exception handling
This is essentially Hazard5, with the `D` and `X` stages merged and the register file brought forward. Many components are reused directly from Hazard5. The particular focus here is on shortening the branch delay, which is one of the weak points in Hazard5's IPC.

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doc/hazard3.pdf
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doc/sections/debug.adoc
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@ -22,6 +22,8 @@ The debug host must use the Program Buffer to access CSRs and memory. This carri
Abstract memory access is not implemented because it offers no better throughput than Program Buffer execution with `abstractauto` for bulk transfers, and non-bulk transfers are still instantaneous from the perspective of the human at the other end of the wire.
The Hazard3 Debug Module has experimental support for multi-core debug. Each core possesses exactly one hardware thread (hart) which is exposed to the debugger. The RISC-V specification does not mandate what mapping is used between the Debug Module hart index `hartsel` and each core's `mhartid` CSR, but a 1:1 match of these values is the least likely to cause issues. Each core's `mhartid` can be configured using the `MHARTID_VAL` parameter during instantiation.
=== Implementation-defined behaviour
Features implemented by DM (beyond the mandatory):