From e6aaf4b801fd3dfdfe09b39ad21a979c5125cf52 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Thu, 6 Oct 2022 00:16:10 +0100 Subject: [PATCH] Avoid IRQ to bus through-path when custom IRQs are disabled --- hdl/hazard3_config.vh | 8 ++++---- hdl/hazard3_csr.v | 12 +++++++++++- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/hdl/hazard3_config.vh b/hdl/hazard3_config.vh index 4d274a1..c102971 100644 --- a/hdl/hazard3_config.vh +++ b/hdl/hazard3_config.vh @@ -72,7 +72,9 @@ parameter EXTENSION_ZIFENCEI = 1, parameter EXTENSION_XH3BEXTM = 1, // EXTENSION_XH3IRQ: Custom preemptive, prioritised interrupt support. Can be -// disabled if an external interrupt controller (e.g. PLIC) is used. +// disabled if an external interrupt controller (e.g. PLIC) is used. If +// disabled, and NUM_IRQS > 1, the external interrupts are simply OR'd into +// mip.meip. parameter EXTENSION_XH3IRQ = 1, // EXTENSION_XH3PMPM: PMPCFGMx CSRs to enforce PMP regions in M-mode without @@ -142,9 +144,7 @@ parameter BREAKPOINT_TRIGGERS = 0, // External interrupt support // NUM_IRQS: Number of external IRQs implemented in meiea, meipa, meifa and -// meipra, if CSR_M_TRAP is enabled. Minimum 1, maximum 512. If -// EXTENSION_XH3IRQ is disabled, NUM_IRQS must be 1, and an external -// interrupt controller (e.g. PLIC) is required. +// meipra, if CSR_M_TRAP is enabled. Minimum 1, maximum 512. parameter NUM_IRQS = 32, // IRQ_PRIORITY_BITS: Number of priority bits implemented for each interrupt diff --git a/hdl/hazard3_csr.v b/hdl/hazard3_csr.v index 669f97c..4ccd250 100644 --- a/hdl/hazard3_csr.v +++ b/hdl/hazard3_csr.v @@ -362,9 +362,19 @@ if (|EXTENSION_XH3IRQ) begin: have_irq_ctrl end else begin: no_irq_ctrl + reg external_irq_pending_r; + + always @ (posedge clk_always_on or negedge rst_n) begin + if (!rst_n) begin + external_irq_pending_r <= 1'b0; + end else begin + external_irq_pending_r <= |irq; + end + end + assign irq_ctrl_rdata = {W_DATA{1'b0}}; - assign external_irq_pending = |irq; assign meicontext_clearts = 1'b0; + assign external_irq_pending = external_irq_pending_r; end endgenerate