tb_cxxrtl: explicitly use set<bool> when there is only one timer IRQ

(i.e. single-core testbench). Avoids some odd behaviour with wide
assignment to single-bit wire from the CXXRTL harness.

test/sim/tb_cxxrtl/Makefile

@@ -14,6 +14,8 @@ SYNTH_CMD += read_verilog -I ../../../hdl -DCONFIG_HEADER="config_$(CONFIG).vh"
 SYNTH_CMD += hierarchy -top $(TOP);
 SYNTH_CMD += write_cxxrtl build-$(DOTF)/dut.cpp
 
+CDEFINES_tb_multicore.f := WIDE_TIMER_IRQ
+
 build-$(DOTF)/dut.cpp: $(shell listfiles $(DOTF))
 	mkdir -p build-$(DOTF)
 	yosys -p '$(SYNTH_CMD)' 2>&1 > build-$(DOTF)/cxxrtl.log
@@ -22,4 +24,4 @@ clean::
 	rm -rf build-$(DOTF) $(TBEXEC)
 
 $(TBEXEC): build-$(DOTF)/dut.cpp tb.cpp
-	clang++ -O3 -std=c++14 $(addprefix -D,$(CDEFINES)) -I $(shell yosys-config --datdir)/include -I build-$(DOTF) tb.cpp -o $(TBEXEC)
+	clang++ -O3 -std=c++14 $(addprefix -D,$(CDEFINES) $(CDEFINES_$(DOTF))) -I $(shell yosys-config --datdir)/include -I build-$(DOTF) tb.cpp -o $(TBEXEC)

test/sim/tb_cxxrtl/tb.cpp

@@ -77,7 +77,16 @@ struct mem_io_state {
 	void step(cxxrtl_design::p_tb &tb) {
 		// Default update logic for mtime, mtimecmp
 		++mtime;
+		// This wire is 1-bit wide on single-core tb, and two bits wide on
+		// multicore tb. Using a set<uint8_t> on the single-core tb results
+		// in bit 8 of mip impossibly being set (bit 7 is the timer IRQ, bit
+		// 8 is hardwired to 0). Seems like a CXXRTL bug but no smaller repro
+		// yet, so use an ifdef for now.
+#ifdef WIDE_TIMER_IRQ
 		tb.p_timer__irq.set<uint8_t>((mtime >= mtimecmp[0]) | (mtime >= mtimecmp[1]) << 1);
+#else
+		tb.p_timer__irq.set<bool>(mtime >= mtimecmp[0]);
+#endif
 	}
 };
 

test/sim/tb_cxxrtl/tb.v

@@ -308,7 +308,7 @@ hazard3_cpu_2port #(
 
 	.irq                        (irq),
 	.soft_irq                   (soft_irq[0]),
-	.timer_irq                  (timer_irq)
+	.timer_irq                  (timer_irq[0])
 );
 
 assign i_hexcl = 1'b0;