Add test for cm.mvsa01/cm.mva01s tearing on IRQs
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Luke Wren
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#include "tb_cxxrtl_io.h"
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#include "hazard3_irq.h"
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#include <stdlib.h>
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// Test intent: check that IRQs interrupting cm.mvsa01 and cm.mva01s do not
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// observe any intermediate states that are disallowed by the ISA manual.
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// These instructions expand to two movs, and an interrupt must not observe
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// the state between the two movs. The Hazard3 implementation should allow
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// the first expanded mov instruction to be interrupted, but not the second.
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uint64_t __attribute__((naked)) foreground_task(uint32_t iters) {
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asm volatile (
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// Move the iters argument to a different areg, as a0/a1 are special
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// wrt cm.mv* instructions
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"mv a4, a0\n"
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"li a5, 0xf00b0000\n"
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// Save s regs which we're about to trash
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"addi sp, sp, -16\n"
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"sw s0, 0(sp)\n"
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"sw s1, 4(sp)\n"
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"sw s2, 8(sp)\n"
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"sw s3, 12(sp)\n"
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// Give each s reg a recognisable token in the upper half, containing
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// a-reg and s-reg index it will be found in:
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"li s0, 0xa0500000\n"
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"li s1, 0xa1510000\n"
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"li s2, 0xa0520000\n"
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"li s3, 0xa1530000\n"
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// Instructions under test: bounce both s-register pairs in and out of
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// a01, incrementing them each time. IRQs are disabled when
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// incrementing the two a registers, to avoid misdiagnosing this as
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// tearing of a cm.mva01s instruction.
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"1:\n"
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".rept 2\n"
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".hword 0xac66\n" // cm.mva01s s0, s1
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"csrci mstatus, 0x8\n" // IRQs OFF
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"addi a0, a0, 1\n"
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"addi a1, a1, 1\n"
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"csrsi mstatus, 0x8\n" // IRQs ON
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".hword 0xac26\n" // cm.mvsa01 s0, s1
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".hword 0xad6e\n" // cm.mva01s s2, s3
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"csrci mstatus, 0x8\n" // IRQs OFF
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"addi a0, a0, 1\n"
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"addi a1, a1, 1\n"
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"csrsi mstatus, 0x8\n" // IRQs ON
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".hword 0xad2e\n" // cm.mvsa01 s2, s3
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".endr\n"
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"addi a4, a4, -1\n"
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"addi a5, a5, 1\n"
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"bgtz a4, 1b\n"
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// Done. We've been counting up in a5 as we count down in a4, so
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// return a5 to confirm we iterated the expected number of times. a1
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// is also returned in a1 -- the lower half should be double the
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// iteration count.
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"csrci mstatus, 0x8\n" // IRQs OFF
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"mv a0, a5\n"
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"lw s0, 0(sp)\n"
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"lw s1, 4(sp)\n"
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"lw s2, 8(sp)\n"
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"lw s3, 12(sp)\n"
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"addi sp, sp, 16\n"
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"ret\n"
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);
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}
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void isr_machine_timer_c(uint32_t a0, uint32_t a1, uint32_t s0, uint32_t s1, uint32_t s2, uint32_t s3) {
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tb_assert((a0 & 0xffffu) == (a1 & 0xffffu), "Low-half tearing of a0,a1");
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tb_assert((s0 & 0xffffu) == (s1 & 0xffffu), "Low-half tearing of s0,s1");
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tb_assert((s2 & 0xffffu) == (s3 & 0xffffu), "Low-half tearing of s2,s3");
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unsigned int dwell = rand() % 301;
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mm_timer->mtimecmp = mm_timer->mtime + dwell;
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}
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// Trampoline into the actual ISR: make a0-1 and s0-3 *in the interrupted
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// code* available as arguments.
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void __attribute__((naked)) isr_machine_timer(void) {
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asm volatile (
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// Save all caller-saved regs
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"addi sp, sp, -80\n"
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"sw ra, 0(sp)\n"
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"sw t0, 4(sp)\n"
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"sw t1, 8(sp)\n"
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"sw t2, 12(sp)\n"
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"sw a0, 16(sp)\n"
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"sw a1, 20(sp)\n"
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"sw a2, 24(sp)\n"
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"sw a3, 28(sp)\n"
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"sw a4, 32(sp)\n"
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"sw a5, 36(sp)\n"
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"sw a6, 40(sp)\n"
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"sw a7, 44(sp)\n"
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"sw t3, 48(sp)\n"
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"sw t4, 52(sp)\n"
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"sw t5, 56(sp)\n"
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"sw t6, 60(sp)\n"
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// Pass first 4 s regs as arguments
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"mv a2, s0\n"
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"mv a3, s1\n"
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"mv a4, s2\n"
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"mv a5, s3\n"
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// Call actual IRQ, written in C
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"jal isr_machine_timer_c\n"
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// Restore caller saves, then return through mepc
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"lw ra, 0(sp)\n"
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"lw t0, 4(sp)\n"
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"lw t1, 8(sp)\n"
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"lw t2, 12(sp)\n"
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"lw a0, 16(sp)\n"
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"lw a1, 20(sp)\n"
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"lw a2, 24(sp)\n"
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"lw a3, 28(sp)\n"
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"lw a4, 32(sp)\n"
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"lw a5, 36(sp)\n"
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"lw a6, 40(sp)\n"
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"lw a7, 44(sp)\n"
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"lw t3, 48(sp)\n"
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"lw t4, 52(sp)\n"
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"lw t5, 56(sp)\n"
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"lw t6, 60(sp)\n"
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"addi sp, sp, 80\n"
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"mret\n"
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);
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}
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int main() {
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tb_puts("Starting\n");
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timer_irq_enable(true);
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// Note we do not globally enable IRQs, the code-under-test enables them
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// once it has set up the necessary register tokens
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const uint32_t expected_iterations = 1000;
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tb_printf("Running %u iterations\n", expected_iterations);
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uint64_t result_a1a0 = foreground_task(expected_iterations);
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uint32_t result_iters = result_a1a0 & 0xffffffffu;
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uint32_t result_a1ctr = result_a1a0 >> 32;
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tb_printf("Result: %08x %08x\n", result_iters, result_a1ctr);
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tb_assert(result_iters == 0xf00b0000u + expected_iterations, "Wrong number of iterations");
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tb_assert(result_a1ctr == (0xa1530000 + 2 * expected_iterations), "Wrong a1 counter value");
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return 0;
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}
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/*EXPECTED-OUTPUT***************************************************************
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Starting
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Running 1000 iterations
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Result: f00b03e8 a15307d0
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*******************************************************************************/
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