From ea5db61582c61c321e329a7c30bd8fee882d0fc8 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sat, 29 May 2021 22:52:50 +0100 Subject: [PATCH] Fix exception being passed to M when X is stalled but M is not (a load which had an unaligned address spuriously during a RAW stall on the result register) --- hdl/hazard3_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hdl/hazard3_core.v b/hdl/hazard3_core.v index 4c62c40..3152cba 100644 --- a/hdl/hazard3_core.v +++ b/hdl/hazard3_core.v @@ -516,13 +516,13 @@ always @ (posedge clk or negedge rst_n) begin {xm_rs1, xm_rs2, xm_rd} <= {d_rs1, d_rs2, d_rd}; // If the transfer is unaligned, make sure it is completely NOP'd on the bus xm_memop <= d_memop | {x_unaligned_addr, 3'h0}; + xm_except <= x_except; if (x_stall || m_trap_enter_vld) begin // Insert bubble xm_rd <= {W_REGADDR{1'b0}}; xm_memop <= MEMOP_NONE; xm_except <= EXCEPT_NONE; end - xm_except <= x_except; end else if (bus_dph_err_d) begin // First phase of 2-phase AHBL error response. Pass the exception along on // this cycle, and on the next cycle the trap entry will be asserted,