From ed6b6a366052513c0d6e757f92089c17ecc598e3 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Thu, 25 Nov 2021 15:16:59 +0000 Subject: [PATCH] Cleanup order of declaration/use of a couple of wires --- hdl/hazard3_core.v | 12 ++++++------ hdl/hazard3_frontend.v | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/hdl/hazard3_core.v b/hdl/hazard3_core.v index 6fd4322..cbaca2f 100644 --- a/hdl/hazard3_core.v +++ b/hdl/hazard3_core.v @@ -276,6 +276,7 @@ reg xm_delay_irq_entry; reg x_stall_raw; wire x_stall_muldiv; wire x_jump_req; +wire m_wfi_stall_clear; // IRQs squeeze in between the instructions in X and M, so in this case X // stalls but M can continue. -> X always stalls on M trap, M *may* stall. @@ -504,7 +505,11 @@ always @ (posedge clk or negedge rst_n) begin end wire [W_ADDR-1:0] m_exception_return_addr; -wire m_wfi_stall_clear; + +wire [W_EXCEPT-1:0] x_except = + x_csr_illegal_access ? EXCEPT_INSTR_ILLEGAL : + x_unaligned_addr && x_memop_write ? EXCEPT_STORE_ALIGN : + x_unaligned_addr && !x_memop_write ? EXCEPT_LOAD_ALIGN : d_except; // If an instruction causes an exceptional condition we do not consider it to have retired. wire x_except_counts_as_retire = x_except == EXCEPT_EBREAK || x_except == EXCEPT_MRET || x_except == EXCEPT_ECALL; @@ -564,11 +569,6 @@ hazard3_csr #( .instr_ret (|x_instr_ret) ); -wire [W_EXCEPT-1:0] x_except = - x_csr_illegal_access ? EXCEPT_INSTR_ILLEGAL : - x_unaligned_addr && x_memop_write ? EXCEPT_STORE_ALIGN : - x_unaligned_addr && !x_memop_write ? EXCEPT_LOAD_ALIGN : d_except; - // Pipe register always @ (posedge clk or negedge rst_n) begin diff --git a/hdl/hazard3_frontend.v b/hdl/hazard3_frontend.v index 691834f..0695f47 100644 --- a/hdl/hazard3_frontend.v +++ b/hdl/hazard3_frontend.v @@ -75,7 +75,7 @@ module hazard3_frontend #( input wire debug_mode, input wire [W_DATA-1:0] dbg_instr_data, input wire dbg_instr_data_vld, - output wire dbg_instr_data_rdy, + output wire dbg_instr_data_rdy ); localparam W_BUNDLE = W_DATA / 2;