Add test for readability of CSRs in U mode. Fix readback value of mstatus.mpp
This commit is contained in:
Luke Wren
parent
ba81b533d2
commit
f033cde874
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@ -495,22 +495,22 @@ always @ (*) begin
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MSTATUS: if (CSR_M_MANDATORY || CSR_M_TRAP) begin
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MSTATUS: if (CSR_M_MANDATORY || CSR_M_TRAP) begin
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decode_match = match_mrw;
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decode_match = match_mrw;
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rdata = {
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rdata = {
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1'b0, // Never any dirty state besides GPRs
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1'b0, // Never any dirty state besides GPRs
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8'd0, // (WPRI)
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8'd0, // (WPRI)
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1'b0, // TSR (Trap SRET), tied 0 if no S mode.
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1'b0, // TSR (Trap SRET), tied 0 if no S mode.
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1'b0, // TW (Timeout Wait), tied 0 if only M mode.
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1'b0, // TW (Timeout Wait), tied 0 if only M mode.
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1'b0, // TVM (trap virtual memory), tied 0 if no S mode.
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1'b0, // TVM (trap virtual memory), tied 0 if no S mode.
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1'b0, // MXR (Make eXecutable Readable), tied 0 if not S mode.
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1'b0, // MXR (Make eXecutable Readable), tied 0 if not S mode.
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1'b0, // SUM, tied 0, we have no S or U mode
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1'b0, // SUM, tied 0, we have no S or U mode
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mstatus_mprv, // MPRV (modify privilege)
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mstatus_mprv, // MPRV (modify privilege)
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4'd0, // XS, FS always "off" (no extension state to clear!)
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4'd0, // XS, FS always "off" (no extension state to clear!)
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{2{m_mode}}, // MPP (M-mode previous privilege), only M and U supported
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{2{mstatus_mpp}}, // MPP (M-mode previous privilege), only M and U supported
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2'd0, // (WPRI)
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2'd0, // (WPRI)
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1'b0, // SPP, tied 0 if S mode not supported
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1'b0, // SPP, tied 0 if S mode not supported
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mstatus_mpie, // Previous interrupt enable
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mstatus_mpie, // Previous interrupt enable
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3'd0, // No S, U
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3'd0, // No S, U
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mstatus_mie, // Interrupt enable
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mstatus_mie, // Interrupt enable
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3'd0 // No S, U
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3'd0 // No S, U
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};
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};
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end
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end
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@ -0,0 +1,348 @@
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#include "tb_cxxrtl_io.h"
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#include "hazard3_csr.h"
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// Check all implemented M-mode and D-mode CSRs are unreadable in U mode.
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// Check that an M-mode trap taken from U mode is able to access the M-mode
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// trap CSRs.
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// These are new (priv-1.12) and may not be recognised by the toolchain:
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#define mconfigptr 0xf15
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#define mstatush 0x310
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// Exceptions here are: medeleg, mideleg, tdata1, dcsr, dpc, dscratch1,
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// dscratch0, dmdata0 (custom). medeleg/mideleg are just a couple of
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// unimplemented registers sprinkled in for a sanity check, and the remainder
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// are D-mode registers.
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//
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// Note we permit reads but not writes to tselect, to work around a logic
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// error in openocd. Planning to implement triggers at some point, so this
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// oddity will vanish.
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/*EXPECTED-OUTPUT***************************************************************
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-> exception, mcause = 2, mpp = 0 // mvendorid
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CSR was f11
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-> exception, mcause = 2, mpp = 0 // marchid
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CSR was f12
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-> exception, mcause = 2, mpp = 0 // mimpid
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CSR was f13
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-> exception, mcause = 2, mpp = 0 // mhartid
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CSR was f14
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-> exception, mcause = 2, mpp = 0 // mconfigptr
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CSR was f15
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-> exception, mcause = 2, mpp = 0 // misa
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CSR was 301
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-> exception, mcause = 2, mpp = 0 // mstatus
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CSR was 300
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-> exception, mcause = 2, mpp = 0 // mstatush
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CSR was 310
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-> exception, mcause = 2, mpp = 0 // mie
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CSR was 304
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-> exception, mcause = 2, mpp = 0 // mip
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CSR was 344
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-> exception, mcause = 2, mpp = 0 // mtvec
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CSR was 305
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-> exception, mcause = 2, mpp = 0 // mscratch
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CSR was 340
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-> exception, mcause = 2, mpp = 0 // mepc
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CSR was 341
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-> exception, mcause = 2, mpp = 0 // mcause
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CSR was 342
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-> exception, mcause = 2, mpp = 0 // mtval
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CSR was 343
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-> exception, mcause = 2, mpp = 0 // mcounteren
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CSR was 306
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-> exception, mcause = 2, mpp = 0 // mcycle
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CSR was b00
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-> exception, mcause = 2, mpp = 0 // mcycleh
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CSR was b80
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-> exception, mcause = 2, mpp = 0 // minstret
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CSR was b02
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-> exception, mcause = 2, mpp = 0 // minstreth
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CSR was b82
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-> exception, mcause = 2, mpp = 0 // mphmcounter3
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CSR was b03
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-> exception, mcause = 2, mpp = 0 // ...
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CSR was b04
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-> exception, mcause = 2, mpp = 0
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CSR was b05
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-> exception, mcause = 2, mpp = 0
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CSR was b06
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-> exception, mcause = 2, mpp = 0
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CSR was b07
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-> exception, mcause = 2, mpp = 0
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CSR was b08
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-> exception, mcause = 2, mpp = 0
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CSR was b09
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-> exception, mcause = 2, mpp = 0
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CSR was b0a
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-> exception, mcause = 2, mpp = 0
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CSR was b0b
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-> exception, mcause = 2, mpp = 0
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CSR was b0c
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-> exception, mcause = 2, mpp = 0
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CSR was b0d
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-> exception, mcause = 2, mpp = 0
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CSR was b0e
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-> exception, mcause = 2, mpp = 0
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CSR was b0f
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-> exception, mcause = 2, mpp = 0
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CSR was b10
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-> exception, mcause = 2, mpp = 0
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CSR was b11
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-> exception, mcause = 2, mpp = 0
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CSR was b12
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-> exception, mcause = 2, mpp = 0
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CSR was b13
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-> exception, mcause = 2, mpp = 0
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CSR was b14
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-> exception, mcause = 2, mpp = 0
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CSR was b15
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-> exception, mcause = 2, mpp = 0
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CSR was b16
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-> exception, mcause = 2, mpp = 0
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CSR was b17
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-> exception, mcause = 2, mpp = 0
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CSR was b18
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-> exception, mcause = 2, mpp = 0
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CSR was b19
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-> exception, mcause = 2, mpp = 0
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CSR was b1a
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-> exception, mcause = 2, mpp = 0
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CSR was b1b
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-> exception, mcause = 2, mpp = 0
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CSR was b1c
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-> exception, mcause = 2, mpp = 0
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CSR was b1d
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-> exception, mcause = 2, mpp = 0
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CSR was b1e
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-> exception, mcause = 2, mpp = 0 // ... mhpmcounter31
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CSR was b1f
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-> exception, mcause = 2, mpp = 0 // mhpmcounter3h
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CSR was b83
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-> exception, mcause = 2, mpp = 0 // ...
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CSR was b84
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-> exception, mcause = 2, mpp = 0
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CSR was b85
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-> exception, mcause = 2, mpp = 0
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CSR was b86
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-> exception, mcause = 2, mpp = 0
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CSR was b87
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-> exception, mcause = 2, mpp = 0
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CSR was b88
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-> exception, mcause = 2, mpp = 0
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CSR was b89
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-> exception, mcause = 2, mpp = 0
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CSR was b8a
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-> exception, mcause = 2, mpp = 0
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CSR was b8b
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-> exception, mcause = 2, mpp = 0
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CSR was b8c
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-> exception, mcause = 2, mpp = 0
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CSR was b8d
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-> exception, mcause = 2, mpp = 0
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CSR was b8e
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-> exception, mcause = 2, mpp = 0
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CSR was b8f
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-> exception, mcause = 2, mpp = 0
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CSR was b90
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-> exception, mcause = 2, mpp = 0
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CSR was b91
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-> exception, mcause = 2, mpp = 0
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CSR was b92
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-> exception, mcause = 2, mpp = 0
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CSR was b93
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-> exception, mcause = 2, mpp = 0
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CSR was b94
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-> exception, mcause = 2, mpp = 0
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CSR was b95
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-> exception, mcause = 2, mpp = 0
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CSR was b96
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-> exception, mcause = 2, mpp = 0
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CSR was b97
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-> exception, mcause = 2, mpp = 0
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CSR was b98
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-> exception, mcause = 2, mpp = 0
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CSR was b99
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-> exception, mcause = 2, mpp = 0
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CSR was b9a
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-> exception, mcause = 2, mpp = 0
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CSR was b9b
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-> exception, mcause = 2, mpp = 0
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CSR was b9c
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-> exception, mcause = 2, mpp = 0
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CSR was b9d
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-> exception, mcause = 2, mpp = 0
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CSR was b9e
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-> exception, mcause = 2, mpp = 0 // ... mhpmcounter31h
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CSR was b9f // followed by U-mode counters, which shouldn't trap...
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-> exception, mcause = 2, mpp = 0 // mcountinhibit
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CSR was 320
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-> exception, mcause = 2, mpp = 0 // mhpmevent3
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CSR was 323
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-> exception, mcause = 2, mpp = 0 // tselect
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CSR was 7a0
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-> exception, mcause = 2, mpp = 0 // tdata1
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CSR was 7a1
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-> exception, mcause = 2, mpp = 0 // dcsr
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CSR was 7b0
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-> exception, mcause = 2, mpp = 0 // dpc
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CSR was 7b1
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-> exception, mcause = 2, mpp = 0 // dscratch0
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CSR was 7b2
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-> exception, mcause = 2, mpp = 0 // dscratch1
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CSR was 7b3
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-> exception, mcause = 2, mpp = 0 // hazard3 dmdata0
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CSR was bff
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-> exception, mcause = 2, mpp = 0 // hazard3 meie0
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CSR was be0
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-> exception, mcause = 2, mpp = 0 // hazard3 meip0
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CSR was fe0
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-> exception, mcause = 2, mpp = 0 // hazard3 mlei
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CSR was fe4
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-> exception, mcause = 3, mpp = 0 // This is the ebreak that ends the test
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*******************************************************************************/
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// This function is run in U mode. It returns to a trampoline that ebreaks to M mode.
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void read_all_csrs() {
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(void)read_csr(mvendorid);
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(void)read_csr(marchid);
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(void)read_csr(mimpid);
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(void)read_csr(mhartid);
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(void)read_csr(mconfigptr);
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(void)read_csr(misa);
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(void)read_csr(mstatus);
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(void)read_csr(mstatush);
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(void)read_csr(mie);
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(void)read_csr(mip);
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(void)read_csr(mtvec);
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(void)read_csr(mscratch);
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(void)read_csr(mepc);
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(void)read_csr(mcause);
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(void)read_csr(mtval);
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(void)read_csr(mcounteren);
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(void)read_csr(mcycle);
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(void)read_csr(mcycleh);
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(void)read_csr(minstret);
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(void)read_csr(minstreth);
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(void)read_csr(mhpmcounter3);
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(void)read_csr(mhpmcounter4);
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(void)read_csr(mhpmcounter5);
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(void)read_csr(mhpmcounter6);
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(void)read_csr(mhpmcounter7);
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(void)read_csr(mhpmcounter8);
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(void)read_csr(mhpmcounter9);
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(void)read_csr(mhpmcounter10);
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(void)read_csr(mhpmcounter11);
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(void)read_csr(mhpmcounter12);
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(void)read_csr(mhpmcounter13);
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(void)read_csr(mhpmcounter14);
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(void)read_csr(mhpmcounter15);
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(void)read_csr(mhpmcounter16);
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(void)read_csr(mhpmcounter17);
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(void)read_csr(mhpmcounter18);
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(void)read_csr(mhpmcounter19);
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(void)read_csr(mhpmcounter20);
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(void)read_csr(mhpmcounter21);
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(void)read_csr(mhpmcounter22);
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(void)read_csr(mhpmcounter23);
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(void)read_csr(mhpmcounter24);
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(void)read_csr(mhpmcounter25);
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(void)read_csr(mhpmcounter26);
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(void)read_csr(mhpmcounter27);
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(void)read_csr(mhpmcounter28);
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(void)read_csr(mhpmcounter29);
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(void)read_csr(mhpmcounter30);
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(void)read_csr(mhpmcounter31);
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(void)read_csr(mhpmcounter3h);
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(void)read_csr(mhpmcounter4h);
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(void)read_csr(mhpmcounter5h);
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(void)read_csr(mhpmcounter6h);
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(void)read_csr(mhpmcounter7h);
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(void)read_csr(mhpmcounter8h);
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(void)read_csr(mhpmcounter9h);
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(void)read_csr(mhpmcounter10h);
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(void)read_csr(mhpmcounter11h);
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(void)read_csr(mhpmcounter12h);
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(void)read_csr(mhpmcounter13h);
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(void)read_csr(mhpmcounter14h);
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(void)read_csr(mhpmcounter15h);
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(void)read_csr(mhpmcounter16h);
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(void)read_csr(mhpmcounter17h);
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(void)read_csr(mhpmcounter18h);
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(void)read_csr(mhpmcounter19h);
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(void)read_csr(mhpmcounter20h);
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(void)read_csr(mhpmcounter21h);
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(void)read_csr(mhpmcounter22h);
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(void)read_csr(mhpmcounter23h);
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(void)read_csr(mhpmcounter24h);
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(void)read_csr(mhpmcounter25h);
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(void)read_csr(mhpmcounter26h);
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(void)read_csr(mhpmcounter27h);
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(void)read_csr(mhpmcounter28h);
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(void)read_csr(mhpmcounter29h);
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(void)read_csr(mhpmcounter30h);
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(void)read_csr(mhpmcounter31h);
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(void)read_csr(cycle);
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(void)read_csr(cycleh);
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(void)read_csr(instret);
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(void)read_csr(instreth);
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(void)read_csr(mcountinhibit);
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(void)read_csr(mhpmevent3);
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(void)read_csr(tselect);
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(void)read_csr(tdata1);
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(void)read_csr(dcsr);
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(void)read_csr(dpc);
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(void)read_csr(dscratch0);
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(void)read_csr(dscratch1);
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(void)read_csr(hazard3_csr_dmdata0);
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(void)read_csr(hazard3_csr_meie0);
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(void)read_csr(hazard3_csr_meip0);
|
||||||
|
(void)read_csr(hazard3_csr_mlei);
|
||||||
|
}
|
||||||
|
|
||||||
|
void __attribute__((naked)) ebreak_trampoline() {
|
||||||
|
asm ("ebreak");
|
||||||
|
}
|
||||||
|
|
||||||
|
int main() {
|
||||||
|
// Make counters accessible to U mode
|
||||||
|
write_csr(mcounteren, -1u);
|
||||||
|
|
||||||
|
// Enter function in U mode, return via ebreak trampoline
|
||||||
|
write_csr(mstatus, read_csr(mstatus) & ~0x1800u);
|
||||||
|
write_csr(mepc, &read_all_csrs);
|
||||||
|
asm (
|
||||||
|
"la ra, ebreak_trampoline\n"
|
||||||
|
"mret\n"
|
||||||
|
);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void __attribute__((interrupt)) handle_exception() {
|
||||||
|
uint32_t mcause = read_csr(mcause);
|
||||||
|
tb_printf("-> exception, mcause = %u, mpp = %u\n", mcause, read_csr(mstatus) >> 11 & 0x3u);
|
||||||
|
write_csr(mcause, 0);
|
||||||
|
if (mcause == 3) {
|
||||||
|
// ebreak -> end of test
|
||||||
|
tb_exit(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t mepc = read_csr(mepc);
|
||||||
|
if ((*(uint16_t*)mepc & 0x3) == 0x3) {
|
||||||
|
tb_printf("CSR was %03x\n", *(uint16_t*)(mepc + 2) >> 4);
|
||||||
|
mepc += 4;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
tb_puts("Exception on 16-bit instruction?!\n");
|
||||||
|
tb_exit(-1);
|
||||||
|
}
|
||||||
|
write_csr(mepc, mepc);
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue