From f7b3097ad65d501c1a890afd39cd8029dce4705e Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Sun, 11 Jul 2021 16:20:39 +0100 Subject: [PATCH] Fix some bugs/typos in DM, add a tb to run read/write vectors against DM, confirm that GPR read/write works --- hdl/debug/dm/hazard3_dm.v | 78 ++++--- test/sim/debug_module_vectors/.gitignore | 2 + test/sim/debug_module_vectors/Makefile | 16 ++ test/sim/debug_module_vectors/gpr.list | 26 +++ test/sim/debug_module_vectors/tb.cpp | 286 +++++++++++++++++++++++ test/sim/debug_module_vectors/tb.f | 4 + test/sim/debug_module_vectors/tb.v | 206 ++++++++++++++++ 7 files changed, 580 insertions(+), 38 deletions(-) create mode 100644 test/sim/debug_module_vectors/.gitignore create mode 100644 test/sim/debug_module_vectors/Makefile create mode 100644 test/sim/debug_module_vectors/gpr.list create mode 100644 test/sim/debug_module_vectors/tb.cpp create mode 100644 test/sim/debug_module_vectors/tb.f create mode 100644 test/sim/debug_module_vectors/tb.v diff --git a/hdl/debug/dm/hazard3_dm.v b/hdl/debug/dm/hazard3_dm.v index 8bb00de..88a82c2 100644 --- a/hdl/debug/dm/hazard3_dm.v +++ b/hdl/debug/dm/hazard3_dm.v @@ -129,6 +129,7 @@ if (N_HARTS > 1) begin: has_hartsel end else begin: has_no_hartsel assign hartsel_next = 1'b0; end +endgenerate always @ (posedge clk or negedge rst_n) begin if (!rst_n) begin @@ -165,7 +166,7 @@ always @ (posedge clk or negedge rst_n) begin dmcontrol_haltreq <= {N_HARTS{1'b0}}; dmcontrol_hartreset <= {N_HARTS{1'b0}}; dmcontrol_resethaltreq <= {N_HARTS{1'b0}}; - end else if dmi_write && dmi_paddr == ADDR_DMCONTROL) begin + end else if (dmi_write && dmi_paddr == ADDR_DMCONTROL) begin dmactive <= dmi_pwdata[0]; dmcontrol_ndmreset <= dmi_pwdata[1]; dmcontrol_haltreq[hartsel_next] <= dmi_pwdata[31]; @@ -217,8 +218,8 @@ always @ (posedge clk or negedge rst_n) begin dmstatus_resumeack <= {N_HARTS{1'b0}}; dmcontrol_resumereq_sticky <= {N_HARTS{1'b0}}; end else begin - dmstatus_resumeack <= dmstatus_resumeack | (dmcontrol_resumereq_sticky & hart_running); - dmcontrol_resumereq_sticky <= dmcontrol_resumereq_sticky & ~hart_running; + dmstatus_resumeack <= dmstatus_resumeack | (dmcontrol_resumereq_sticky & hart_running & hart_available); + dmcontrol_resumereq_sticky <= dmcontrol_resumereq_sticky & ~(hart_running & hart_available); // TODO this is because our "running" is actually just "not debug mode" // dmcontrol.resumereq: if (dmi_write && dmi_paddr == ADDR_DMCONTROL && dmi_pwdata[30]) begin dmcontrol_resumereq_sticky[hartsel_next] <= 1'b1; @@ -227,7 +228,7 @@ always @ (posedge clk or negedge rst_n) begin end end -assign hart_req_resume = ~dmstatus_resumeack; +assign hart_req_resume = dmcontrol_resumereq_sticky; // ---------------------------------------------------------------------------- // Abstract command data registers @@ -263,7 +264,7 @@ always @ (posedge clk or negedge rst_n) begin end else if (!dmactive) begin abstractauto_autoexecdata <= 1'b0; end else if (dmi_write && dmi_paddr == ADDR_ABSTRACTAUTO) begin - abstractauto_autoexecdata <= pwdata[1]; + abstractauto_autoexecdata <= dmi_pwdata[1]; end end @@ -292,11 +293,11 @@ localparam CMDERR_HALTRESUME = 3'h4; reg [2:0] abstractcs_cmderr; reg [W_STATE-1:0] acmd_state; -assign abstracts_busy = acmd_state != S_IDLE; +assign abstractcs_busy = acmd_state != S_IDLE; wire start_abstract_cmd = abstractcs_cmderr == CMDERR_OK && !abstractcs_busy && ( (dmi_write && dmi_paddr == ADDR_COMMAND) || - ((dmi_write || dmi_read) && abstractauto_autoexecdata && dmi_paddr == ADDR_DATA0 + ((dmi_write || dmi_read) && abstractauto_autoexecdata && dmi_paddr == ADDR_DATA0) ); wire dmi_access_illegal_when_busy = @@ -316,7 +317,7 @@ wire acmd_unsupported = wire acmd_postexec = dmi_pwdata[18]; wire acmd_transfer = dmi_pwdata[17]; wire acmd_write = dmi_pwdata[16]; -wire [4:0] acmd_regno = dmi_pwdata[4:0] +wire [4:0] acmd_regno = dmi_pwdata[4:0]; reg acmd_postexec_r; reg [4:0] acmd_regno_r; @@ -324,81 +325,81 @@ reg [4:0] acmd_regno_r; always @ (posedge clk or negedge rst_n) begin if (!rst_n) begin abstractcs_cmderr <= CMDERR_OK; - abstractcs_state <= S_IDLE; + acmd_state <= S_IDLE; acmd_postexec_r <= 1'b0; acmd_regno_r <= 5'h0; end else if (!dmactive) begin abstractcs_cmderr <= CMDERR_OK; - abstractcs_state <= S_IDLE; + acmd_state <= S_IDLE; end else begin - if (abstractcs_cmderr == CMDERR_OK && abstracts_busy && dmi_access_illegal_when_busy) + if (abstractcs_cmderr == CMDERR_OK && abstractcs_busy && dmi_access_illegal_when_busy) abstractcs_cmderr <= CMDERR_BUSY; - if (state != S_IDLE && hart_instr_caught_exception) + if (acmd_state != S_IDLE && hart_instr_caught_exception) abstractcs_cmderr <= CMDERR_EXCEPTION; case (acmd_state) S_IDLE: begin if (start_abstract_cmd) begin if (!hart_halted[hartsel] || !hart_available[hartsel]) begin - abstracts_cmderr <= CMDERR_HALTRESUME; - end else if (acmd_unsupported) + abstractcs_cmderr <= CMDERR_HALTRESUME; + end else if (acmd_unsupported) begin abstractcs_cmderr <= CMDERR_UNSUPPORTED; end else begin acmd_postexec_r <= acmd_postexec; acmd_regno_r <= acmd_regno; if (acmd_transfer && acmd_write) - state <= S_ISSUE_REGWRITE; + acmd_state <= S_ISSUE_REGWRITE; else if (acmd_transfer && !acmd_write) - state <= S_ISSUE_REGREAD; + acmd_state <= S_ISSUE_REGREAD; else if (acmd_postexec) - state <= S_ISSUE_PROGBUF0; + acmd_state <= S_ISSUE_PROGBUF0; else - state <= S_IDLE; + acmd_state <= S_IDLE; end end end S_ISSUE_REGREAD: begin if (hart_instr_data_rdy[hartsel]) - state <= S_ISSUE_REGEBREAK; + acmd_state <= S_ISSUE_REGEBREAK; end S_ISSUE_REGWRITE: begin if (hart_instr_data_rdy[hartsel]) - state <= S_ISSUE_REGEBREAK; + acmd_state <= S_ISSUE_REGEBREAK; end S_ISSUE_REGEBREAK: begin if (hart_instr_data_rdy[hartsel]) - state <= S_WAIT_REGEBREAK + acmd_state <= S_WAIT_REGEBREAK; end S_WAIT_REGEBREAK: begin if (hart_instr_caught_ebreak) begin if (acmd_postexec_r) - state <= S_ISSUE_PROGBUF0; + acmd_state <= S_ISSUE_PROGBUF0; else - state <= S_IDLE; + acmd_state <= S_IDLE; end end S_ISSUE_PROGBUF0: begin if (hart_instr_data_rdy[hartsel]) - state <= S_ISSUE_PROGBUF1; + acmd_state <= S_ISSUE_PROGBUF1; end S_ISSUE_PROGBUF1: begin if (hart_instr_caught_exception || hart_instr_caught_ebreak) begin - state <= S_IDLE; + acmd_state <= S_IDLE; end else if (hart_instr_data_rdy[hartsel]) begin - state <= S_ISSUE_IMPEBREAK; + acmd_state <= S_ISSUE_IMPEBREAK; end end S_ISSUE_IMPEBREAK: begin if (hart_instr_caught_exception || hart_instr_caught_ebreak) begin - state <= S_IDLE; + acmd_state <= S_IDLE; end else if (hart_instr_data_rdy[hartsel]) begin - state <= S_WAIT_IMPEBREAK; + acmd_state <= S_WAIT_IMPEBREAK; end end S_WAIT_IMPEBREAK: begin if (hart_instr_caught_exception || hart_instr_caught_ebreak) begin - state <= S_IDLE; + acmd_state <= S_IDLE; end end endcase @@ -406,20 +407,21 @@ always @ (posedge clk or negedge rst_n) begin end assign hart_instr_data_vld = {{N_HARTS{1'b0}}, - state == S_ISSUE_REGREAD || state == S_ISSUE_REGWRITE || state == S_ISSUE_REGEBREAK || - state == S_ISSUE_PROGBUF0 || state == S_ISSUE_PROGBUF1 || state == S_ISSUE_IMPEBREAK + acmd_state == S_ISSUE_REGREAD || acmd_state == S_ISSUE_REGWRITE || acmd_state == S_ISSUE_REGEBREAK || + acmd_state == S_ISSUE_PROGBUF0 || acmd_state == S_ISSUE_PROGBUF1 || acmd_state == S_ISSUE_IMPEBREAK } << hartsel; assign hart_instr_data = {N_HARTS{ - state == S_ISSUE_REGWRITE ? 32'h7b202073 | {20'd0, acmd_regno_r, 7'd0} : // csrr xx, data0 - state == S_ISSUE_REGREAD ? 32'h7b201073 | {12'd0, acmd_regno_r, 15'd0} : // csrw data0, xx - state == S_ISSUE_PROGBUF0 ? progbuf0 : - state == S_ISSUE_PROGBUF1 ? progbuf1 : - 32'h00100073 // ebreak + acmd_state == S_ISSUE_REGWRITE ? 32'h7b202073 | {20'd0, acmd_regno_r, 7'd0} : // csrr xx, data0 + acmd_state == S_ISSUE_REGREAD ? 32'h7b201073 | {12'd0, acmd_regno_r, 15'd0} : // csrw data0, xx + acmd_state == S_ISSUE_PROGBUF0 ? progbuf0 : + acmd_state == S_ISSUE_PROGBUF1 ? progbuf1 : + 32'h00100073 // ebreak }}; // ---------------------------------------------------------------------------- // DMI read data mux + always @ (*) begin case (dmi_paddr) ADDR_DATA0: dmi_prdata = hart_data0_rdata[hartsel * XLEN +: XLEN]; @@ -430,7 +432,7 @@ always @ (*) begin 1'b0, // ackhavereset is a W1 field 1'b0, // reserved 1'b0, // hasel hardwired 0 (no array mask) - {{10-W_HARTSEL{1'b0}}, hartsel} // hartsello + {{10-W_HARTSEL{1'b0}}, hartsel}, // hartsello 10'h0, // hartselhi 2'h0, // reserved 2'h0, // set/clrresethaltreq are W1 fields @@ -444,7 +446,7 @@ always @ (*) begin {2{dmstatus_havereset[hartsel]}}, // allhavereset, anyhavereset {2{dmstatus_resumeack[hartsel]}}, // allresumeack, anyresumeack {2{hartsel >= N_HARTS}}, // allnonexistent, anynonexistent - {2{!hart_available[hartsel}}, // allunavail, anyunavail + {2{!hart_available[hartsel]}}, // allunavail, anyunavail {2{hart_running[hartsel]}}, // allrunning, anyrunning {2{hart_halted[hartsel]}}, // allhalted, anyhalted 1'b1, // authenticated diff --git a/test/sim/debug_module_vectors/.gitignore b/test/sim/debug_module_vectors/.gitignore new file mode 100644 index 0000000..719db5b --- /dev/null +++ b/test/sim/debug_module_vectors/.gitignore @@ -0,0 +1,2 @@ +tb +dut.cpp diff --git a/test/sim/debug_module_vectors/Makefile b/test/sim/debug_module_vectors/Makefile new file mode 100644 index 0000000..6c6d4b1 --- /dev/null +++ b/test/sim/debug_module_vectors/Makefile @@ -0,0 +1,16 @@ +TOP := tb + +all: tb + +SYNTH_CMD += read_verilog -I ../../../hdl $(shell listfiles tb.f); +SYNTH_CMD += prep -flatten -top $(TOP); async2sync; +SYNTH_CMD += write_cxxrtl dut.cpp + +dut.cpp: + yosys -p "$(SYNTH_CMD)" 2>&1 > cxxrtl.log + +clean:: + rm -f dut.cpp cxxrtl.log tb + +tb: dut.cpp + clang++ -O3 -std=c++14 $(addprefix -D,$(CDEFINES)) -I $(shell yosys-config --datdir)/include tb.cpp -o tb diff --git a/test/sim/debug_module_vectors/gpr.list b/test/sim/debug_module_vectors/gpr.list new file mode 100644 index 0000000..1171477 --- /dev/null +++ b/test/sim/debug_module_vectors/gpr.list @@ -0,0 +1,26 @@ +# data0 is at 0x04 +# command is at 0x17 +# command for reg write is 0x00231000 + reg +# command for reg read is 0x00221000 + reg + +# Turn on dm +w 0x10 1 +# Request halt +w 0x10 0x80000001 +# Read back halt status +i 30 +r 0x11 + +# write to registers a0, a1 +w 0x04 0x1234 +w 0x17 0x00231008 +w 0x04 0x5678 +w 0x17 0x00231009 + +# Read them back +w 0x17 0x00221008 +r 0x04 +w 0x17 0x00221009 +r 0x04 + +x diff --git a/test/sim/debug_module_vectors/tb.cpp b/test/sim/debug_module_vectors/tb.cpp new file mode 100644 index 0000000..57f43dd --- /dev/null +++ b/test/sim/debug_module_vectors/tb.cpp @@ -0,0 +1,286 @@ +#include +#include +#include +#include +#include +#include +#include + +// Device-under-test model generated by CXXRTL: +#include "dut.cpp" +#include + +static const unsigned int MEM_SIZE = 16 * 1024 * 1024; +uint8_t mem[MEM_SIZE]; + +static const unsigned int IO_BASE = 0x80000000; +enum { + IO_PRINT_CHAR = 0, + IO_PRINT_U32 = 4, + IO_EXIT = 8 +}; + +const char *help_str = +"Usage: tb binfile cmdlist [vcdfile] [--dump start end] [--cycles n]\n" +" binfile : Binary to load into start of memory\n" +" cmdlist : Debug module command list file\n" +" vcdfile : Path to dump waveforms to\n" +" --dump start end : Print out memory contents between start and end (exclusive)\n" +" after execution finishes. Can be passed multiple times.\n" +" --cycles n : Maximum number of cycles to run before exiting.\n" +; + +void exit_help(std::string errtext = "") { + std::cerr << errtext << help_str; + exit(-1); +} + +enum cmdstate { + S_IDLE = 0, + S_WRITE_SETUP, + S_WRITE_ACCESS, + S_READ_SETUP, + S_READ_ACCESS +}; + +int main(int argc, char **argv) { + + if (argc < 3) + exit_help(); + + bool dump_waves = false; + std::string waves_path; + std::vector> dump_ranges; + int64_t max_cycles = 100000; + + for (int i = 3; i < argc; ++i) { + std::string s(argv[i]); + if (i == 3 && s.rfind("--", 0) != 0) { + // Optional positional argument: vcdfile + dump_waves = true; + waves_path = s; + } + else if (s == "--dump") { + if (argc - i < 3) + exit_help("Option --dump requires 2 arguments\n"); + dump_ranges.push_back(std::pair( + std::stoul(argv[i + 1], 0, 0), + std::stoul(argv[i + 2], 0, 0) + ));; + i += 2; + } + else if (s == "--cycles") { + if (argc - i < 2) + exit_help("Option --cycles requires an argument\n"); + max_cycles = std::stol(argv[i + 1], 0, 0); + i += 1; + } + else { + std::cerr << "Unrecognised argument " << s << "\n"; + exit_help(""); + } + } + + cxxrtl_design::p_tb top; + + std::fill(std::begin(mem), std::end(mem), 0); + + std::ifstream fd(argv[1], std::ios::binary | std::ios::ate); + std::streamsize bin_size = fd.tellg(); + if (bin_size > MEM_SIZE) { + std::cerr << "Binary file (" << bin_size << " bytes) is larger than memory (" << MEM_SIZE << " bytes)\n"; + return -1; + } + fd.seekg(0, std::ios::beg); + fd.read((char*)mem, bin_size); + + std::ifstream cmdfile(argv[2]); + + std::ofstream waves_fd; + cxxrtl::vcd_writer vcd; + if (dump_waves) { + waves_fd.open(waves_path); + cxxrtl::debug_items all_debug_items; + top.debug_info(all_debug_items); + vcd.timescale(1, "us"); + vcd.add(all_debug_items); + } + + bool bus_trans = false; + bool bus_write = false; + bool bus_trans_i = false; + uint32_t bus_addr_i = 0; + uint32_t bus_addr = 0; + uint8_t bus_size = 0; + // Never generate bus stalls + top.p_i__hready.set(true); + top.p_d__hready.set(true); + + // Reset + initial clock pulse + top.step(); + top.p_clk.set(true); + top.step(); + top.p_clk.set(false); + top.p_rst__n.set(true); + top.step(); + + cmdstate state = S_IDLE; + int idle_counter = 0; + + for (int64_t cycle = 0; cycle < max_cycles; ++cycle) { + top.p_clk.set(false); + top.step(); + if (dump_waves) + vcd.sample(cycle * 2); + top.p_clk.set(true); + top.step(); + + bool got_exit_cmd = false; + + switch (state) { + case S_IDLE: + if (idle_counter > 0) { + --idle_counter; + } + else { + std::string line; + do { + if (!std::getline(cmdfile, line)) + line = "i 1000"; + } while (line.length() == 0 || line[0] == '#'); + + std::istringstream iss(line); + iss >> std::setbase(0); + std::string verb; + iss >> verb; + if (verb == "i") { + iss >> idle_counter; + printf("i %d\n", idle_counter); + } + else if (verb == "w") { + uint32_t addr, data; + iss >> addr; + iss >> data; + top.p_dmi__paddr.set(addr); + top.p_dmi__pwdata.set(data); + top.p_dmi__psel.set(true); + top.p_dmi__pwrite.set(true); + state = S_WRITE_SETUP; + printf("w %02x: %08x\n", addr, data); + } + else if (verb == "r") { + uint32_t addr; + iss >> addr; + top.p_dmi__paddr.set(addr); + top.p_dmi__psel.set(true); + top.p_dmi__pwrite.set(false); + state = S_READ_SETUP; + } + else if (verb == "x") { + got_exit_cmd = true; + } + else { + std::cerr << "Unrecognised verb " << verb << "\n"; + got_exit_cmd = true; + } + } + break; + case S_READ_SETUP: + top.p_dmi__penable.set(true); + state = S_READ_ACCESS; + break; + case S_READ_ACCESS: + top.p_dmi__penable.set(false); + top.p_dmi__psel.set(false); + printf("r %02x: %08x\n", top.p_dmi__paddr.get(), top.p_dmi__prdata.get()); + state = S_IDLE; + idle_counter = 10; + break; + case S_WRITE_SETUP: + top.p_dmi__penable.set(true); + state = S_WRITE_ACCESS; + break; + case S_WRITE_ACCESS: + top.p_dmi__penable.set(false); + top.p_dmi__psel.set(false); + top.p_dmi__pwrite.set(false); + state = S_IDLE; + idle_counter = 10; + break; + default: + state = S_IDLE; + break; + } + + // Handle current data phase, then move current address phase to data phase + uint32_t rdata = 0; + if (bus_trans && bus_write) { + uint32_t wdata = top.p_d__hwdata.get(); + if (bus_addr <= MEM_SIZE) { + unsigned int n_bytes = 1u << bus_size; + // Note we are relying on hazard3's byte lane replication + for (unsigned int i = 0; i < n_bytes; ++i) { + mem[bus_addr + i] = wdata >> (8 * i) & 0xffu; + } + } + else if (bus_addr == IO_BASE + IO_PRINT_CHAR) { + putchar(wdata); + } + else if (bus_addr == IO_BASE + IO_PRINT_U32) { + printf("%08x\n", wdata); + } + else if (bus_addr == IO_BASE + IO_EXIT) { + printf("CPU requested halt. Exit code %d\n", wdata); + printf("Ran for %ld cycles\n", cycle + 1); + break; + } + } + else if (bus_trans && !bus_write) { + if (bus_addr <= MEM_SIZE) { + bus_addr &= ~0x3u; + rdata = + (uint32_t)mem[bus_addr] | + mem[bus_addr + 1] << 8 | + mem[bus_addr + 2] << 16 | + mem[bus_addr + 3] << 24; + } + } + top.p_d__hrdata.set(rdata); + if (bus_trans_i) { + bus_addr_i &= ~0x3u; + top.p_i__hrdata.set( + (uint32_t)mem[bus_addr_i] | + mem[bus_addr_i + 1] << 8 | + mem[bus_addr_i + 2] << 16 | + mem[bus_addr_i + 3] << 24 + ); + } + + bus_trans = top.p_d__htrans.get() >> 1; + bus_write = top.p_d__hwrite.get(); + bus_size = top.p_d__hsize.get(); + bus_addr = top.p_d__haddr.get(); + bus_trans_i = top.p_i__htrans.get() >> 1; + bus_addr_i = top.p_i__haddr.get(); + + if (dump_waves) { + // The extra step() is just here to get the bus responses to line up nicely + // in the VCD (hopefully is a quick update) + top.step(); + vcd.sample(cycle * 2 + 1); + waves_fd << vcd.buffer; + vcd.buffer.clear(); + } + if (got_exit_cmd) + break; + } + + for (auto r : dump_ranges) { + printf("Dumping memory from %08x to %08x:\n", r.first, r.second); + for (int i = 0; i < r.second - r.first; ++i) + printf("%02x%c", mem[r.first + i], i % 16 == 15 ? '\n' : ' '); + printf("\n"); + } + + return 0; +} diff --git a/test/sim/debug_module_vectors/tb.f b/test/sim/debug_module_vectors/tb.f new file mode 100644 index 0000000..b5b9508 --- /dev/null +++ b/test/sim/debug_module_vectors/tb.f @@ -0,0 +1,4 @@ +file tb.v + +list $HDL/hazard3.f +file $HDL/debug/dm/hazard3_dm.v diff --git a/test/sim/debug_module_vectors/tb.v b/test/sim/debug_module_vectors/tb.v new file mode 100644 index 0000000..5e46981 --- /dev/null +++ b/test/sim/debug_module_vectors/tb.v @@ -0,0 +1,206 @@ +// This is not really a "testbench", just an integration of CPU + DM for a +// CXXRTL test to poke at + +module tb #( + parameter W_DATA = 32, + parameter W_ADDR = 32, + parameter NUM_IRQ = 16 +) ( + // Global signals + input wire clk, + input wire rst_n, + + // Instruction fetch port + output wire [W_ADDR-1:0] i_haddr, + output wire i_hwrite, + output wire [1:0] i_htrans, + output wire [2:0] i_hsize, + output wire [2:0] i_hburst, + output wire [3:0] i_hprot, + output wire i_hmastlock, + input wire i_hready, + input wire i_hresp, + output wire [W_DATA-1:0] i_hwdata, + input wire [W_DATA-1:0] i_hrdata, + + // Load/store port + output wire [W_ADDR-1:0] d_haddr, + output wire d_hwrite, + output wire [1:0] d_htrans, + output wire [2:0] d_hsize, + output wire [2:0] d_hburst, + output wire [3:0] d_hprot, + output wire d_hmastlock, + input wire d_hready, + input wire d_hresp, + output wire [W_DATA-1:0] d_hwdata, + input wire [W_DATA-1:0] d_hrdata, + + // Debug module interface + input wire dmi_psel, + input wire dmi_penable, + input wire dmi_pwrite, + input wire [7:0] dmi_paddr, + input wire [31:0] dmi_pwdata, + output reg [31:0] dmi_prdata, + output wire dmi_pready, + output wire dmi_pslverr, + + // Level-sensitive interrupt sources + input wire [NUM_IRQ-1:0] irq, // -> mip.meip + input wire soft_irq, // -> mip.msip + input wire timer_irq // -> mip.mtip +); + +localparam N_HARTS = 1; +localparam XLEN = 32; + +wire sys_reset_req; +wire sys_reset_done; +wire [N_HARTS-1:0] hart_reset_req; +wire [N_HARTS-1:0] hart_reset_done; + +wire [N_HARTS-1:0] hart_req_halt; +wire [N_HARTS-1:0] hart_req_halt_on_reset; +wire [N_HARTS-1:0] hart_req_resume; +wire [N_HARTS-1:0] hart_halted; +wire [N_HARTS-1:0] hart_running; + +wire [N_HARTS*XLEN-1:0] hart_data0_rdata; +wire [N_HARTS*XLEN-1:0] hart_data0_wdata; +wire [N_HARTS-1:0] hart_data0_wen; + +wire [N_HARTS*XLEN-1:0] hart_instr_data; +wire [N_HARTS-1:0] hart_instr_data_vld; +wire [N_HARTS-1:0] hart_instr_data_rdy; +wire [N_HARTS-1:0] hart_instr_caught_exception; +wire [N_HARTS-1:0] hart_instr_caught_ebreak; + +hazard3_dm #( + .N_HARTS (N_HARTS), + .NEXT_DM_ADDR (0) +) dm ( + .clk (clk), + .rst_n (rst_n), + + .dmi_psel (dmi_psel), + .dmi_penable (dmi_penable), + .dmi_pwrite (dmi_pwrite), + .dmi_paddr (dmi_paddr), + .dmi_pwdata (dmi_pwdata), + .dmi_prdata (dmi_prdata), + .dmi_pready (dmi_pready), + .dmi_pslverr (dmi_pslverr), + + .sys_reset_req (sys_reset_req), + .sys_reset_done (sys_reset_done), + .hart_reset_req (hart_reset_req), + .hart_reset_done (hart_reset_done), + + .hart_req_halt (hart_req_halt), + .hart_req_halt_on_reset (hart_req_halt_on_reset), + .hart_req_resume (hart_req_resume), + .hart_halted (hart_halted), + .hart_running (hart_running), + + .hart_data0_rdata (hart_data0_rdata), + .hart_data0_wdata (hart_data0_wdata), + .hart_data0_wen (hart_data0_wen), + + .hart_instr_data (hart_instr_data), + .hart_instr_data_vld (hart_instr_data_vld), + .hart_instr_data_rdy (hart_instr_data_rdy), + .hart_instr_caught_exception (hart_instr_caught_exception), + .hart_instr_caught_ebreak (hart_instr_caught_ebreak) +); + + +// Generate resynchronised reset for CPU based on upstream reset and +// on reset requests from DM. + +wire assert_cpu_reset = !rst_n || sys_reset_req || hart_reset_req[0]; + +reg [1:0] cpu_reset_sync; +wire rst_n_cpu = cpu_reset_sync[1]; + +always @ (posedge clk or posedge assert_cpu_reset) + if (assert_cpu_reset) + cpu_reset_sync <= 2'b00; + else + cpu_reset_sync <= (cpu_reset_sync << 1) | 2'b01; + +// Still some work to be done on the reset handshake -- this ought to be +// resynchronised to DM's reset domain here, and the DM should wait for a +// rising edge after it has asserted the reset pulse, to make sure the tail +// of the previous "done" is not passed on. +assign sys_reset_done = rst_n_cpu; +assign hart_reset_done = rst_n_cpu; + + +hazard3_cpu_2port #( + .RESET_VECTOR (32'hc0), + .MTVEC_INIT (32'h00), + .EXTENSION_C (1), + .EXTENSION_M (1), + .CSR_M_MANDATORY (1), + .CSR_M_TRAP (1), + .CSR_COUNTER (1), + .DEBUG_SUPPORT (1), + .NUM_IRQ (NUM_IRQ), + .MVENDORID_VAL (32'hdeadbeef), + .MARCHID_VAL (32'hfeedf00d), + .MIMPID_VAL (32'h12345678), + .MHARTID_VAL (32'h0), + .REDUCED_BYPASS (0), + .MULDIV_UNROLL (2), + .MUL_FAST (1), +) cpu ( + .clk (clk), + .rst_n (rst_n_cpu), + + .i_haddr (i_haddr), + .i_hwrite (i_hwrite), + .i_htrans (i_htrans), + .i_hsize (i_hsize), + .i_hburst (i_hburst), + .i_hprot (i_hprot), + .i_hmastlock (i_hmastlock), + .i_hready (i_hready), + .i_hresp (i_hresp), + .i_hwdata (i_hwdata), + .i_hrdata (i_hrdata), + + .d_haddr (d_haddr), + .d_hwrite (d_hwrite), + .d_htrans (d_htrans), + .d_hsize (d_hsize), + .d_hburst (d_hburst), + .d_hprot (d_hprot), + .d_hmastlock (d_hmastlock), + .d_hready (d_hready), + .d_hresp (d_hresp), + .d_hwdata (d_hwdata), + .d_hrdata (d_hrdata), + + .dbg_req_halt (hart_req_halt), + .dbg_req_halt_on_reset (hart_req_halt_on_reset), + .dbg_req_resume (hart_req_resume), + .dbg_halted (hart_halted), + .dbg_running (hart_running), + + .dbg_data0_rdata (hart_data0_rdata), + .dbg_data0_wdata (hart_data0_wdata), + .dbg_data0_wen (hart_data0_wen), + + .dbg_instr_data (hart_instr_data), + .dbg_instr_data_vld (hart_instr_data_vld), + .dbg_instr_data_rdy (hart_instr_data_rdy), + .dbg_instr_caught_exception (hart_instr_caught_exception), + .dbg_instr_caught_ebreak (hart_instr_caught_ebreak), + + .irq (irq), + .soft_irq (soft_irq), + .timer_irq (timer_irq) +); + +endmodule