From f9dafa38676b2420d6db316f1bc88eee7232fc63 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Mon, 22 Aug 2022 09:25:37 +0100 Subject: [PATCH] Update readme --- Readme.md | 4 ---- 1 file changed, 4 deletions(-) diff --git a/Readme.md b/Readme.md index 1692910..f82c314 100644 --- a/Readme.md +++ b/Readme.md @@ -21,10 +21,6 @@ This repository also contains a compliant RISC-V Debug Module for Hazard3, which There is an [example SoC integration](example_soc/soc/example_soc.v), showing how these components can be assembled to create a minimal system with a JTAG-enabled RISC-V processor, some RAM and a serial port. -The following are planned for future implementation: - -* Debug trigger unit (breakpoint-only) - Hazard3 is still under development. # Links to Specifications