Hopefully fix case where we jump to the address immediately after a
halfword-sized word-aligned predicted-taken branch, and an address-phase hold causes the jump target to go to the fetch address counter, causing a spurious BTB match on the branch.
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@ -712,7 +712,7 @@ wire [W_ADDR-1:0] x_jump_target = x_addr_sum & ~32'h1;
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wire x_jump_misaligned = ~|EXTENSION_C && x_addr_sum[1];
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wire x_branch_cmp_noinvert;
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wire x_branch_was_predicted = |BRANCH_PREDICTOR && fd_cir_predbranch[fd_cir[1:0] == 2'b11];
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wire x_branch_was_predicted = |BRANCH_PREDICTOR && fd_cir_predbranch[0];
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wire x_branch_cmp = x_branch_cmp_noinvert ^ x_branch_was_predicted;
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generate
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@ -95,6 +95,7 @@ localparam FIFO_DEPTH = 2;
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wire jump_now = jump_target_vld && jump_target_rdy;
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reg [1:0] mem_data_hwvld;
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// Mark data as containing a predicted-taken branch instruction so that
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// mispredicts can be recovered -- need to track both halfwords so that we
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// can mark the entire instruction, and nothing but the instruction:
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@ -225,13 +226,20 @@ assign btb_target_addr_out = btb_target_addr;
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reg [W_ADDR-1:0] fetch_addr;
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reg fetch_priv;
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reg btb_prev_start_of_overhanging;
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reg [1:0] mem_aph_hwvld;
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wire btb_match_word = |BRANCH_PREDICTOR && btb_valid && (
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fetch_addr[W_ADDR-1:2] == btb_src_addr[W_ADDR-1:2]
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);
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// Catch case where predicted-taken branch instruction extends into next word:
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wire btb_src_overhanging = btb_src_size && btb_src_addr[1];
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wire btb_match_current_addr = btb_match_word && !btb_src_overhanging;
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// Suppress case where we have jumped immediately after a word-aligned halfword-sized
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// branch, and the jump target went into fetch_addr due to an address-phase hold:
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wire btb_jumped_beyond = !btb_src_size && !btb_src_addr[1] && !mem_aph_hwvld[0];
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wire btb_match_current_addr = btb_match_word && !btb_src_overhanging && !btb_jumped_beyond;
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wire btb_match_next_addr = btb_match_word && btb_src_overhanging;
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wire btb_match_now = btb_match_current_addr || btb_prev_start_of_overhanging;
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@ -353,8 +361,6 @@ always @ (posedge clk or negedge rst_n) begin
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end
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end
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reg [1:0] mem_aph_hwvld;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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mem_data_hwvld <= 2'b11;
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