colin
/
Hazard3
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

PPA: simplify generation of uop_atomic and uop_seq_end flags in instr_decompress to be independent of most instruction bits. Add some new assertions on behaviour of uop signals outside of uop sequences.

This commit is contained in:
Luke Wren 2024-05-18 16:55:53 +01:00
parent c550d79047
commit fbacbe82a7
1 changed files with 8 additions and 20 deletions

28
hdl/hazard3_instr_decompress.v
View File

@ -114,10 +114,12 @@ function [31:0] rfmt_rs2; input [4:0] rs2; begin rfmt_rs2 = {7'h00, rs2, 20'h000
reg [3:0] uop_ctr;
reg [3:0] uop_ctr_nxt;
reg in_uop_seq;
reg uop_seq_end;
reg uop_atomic;
reg uop_no_pc_update;
wire zcmp_is_pushpop = instr_in[12];
wire uop_seq_end = |EXTENSION_ZCMP && (zcmp_is_pushpop ? uop_ctr == 4'hf : uop_ctr[0]);
wire uop_atomic = |EXTENSION_ZCMP && (zcmp_is_pushpop ? uop_ctr >= 4'he : uop_ctr[0]);
assign instr_out_is_uop = in_uop_seq;
assign instr_out_is_final_uop = uop_seq_end;
assign instr_out_uop_atomic = uop_atomic;
@ -181,18 +183,14 @@ end else begin: instr_decompress
instr_is_32bit = 1'b1;
instr_out = instr_in;
invalid = 1'b0;
uop_seq_end = 1'b0;
in_uop_seq = 1'b0;
uop_atomic = 1'b0;
uop_no_pc_update = 1'b0;
uop_ctr_nxt = uop_ctr;
end else begin
instr_is_32bit = 1'b0;
instr_out = 32'h0;
invalid = 1'b0;
uop_seq_end = 1'b0;
in_uop_seq = 1'b0;
uop_atomic = 1'b0;
uop_no_pc_update = 1'b0;
uop_ctr_nxt = uop_ctr;
casez (instr_in[15:0])
@ -303,7 +301,6 @@ end else begin: instr_decompress
invalid = 1'b1;
end else if (uop_ctr == 4'hf) begin
in_uop_seq = 1'b1;
uop_seq_end = 1'b1;
uop_ctr_nxt = 4'h0;
instr_out = zcmp_push_stack_adj_instr;
end else begin
@ -320,9 +317,7 @@ end else begin: instr_decompress
invalid = 1'b1;
end else if (uop_ctr == 4'hf) begin
in_uop_seq = 1'b1;
uop_seq_end = 1'b1;
uop_ctr_nxt = 4'h0;
uop_atomic = 1'b1;
instr_out = zcmp_pop_stack_adj_instr;
end else begin
in_uop_seq = 1'b1;
@ -341,14 +336,11 @@ end else begin: instr_decompress
// we mark this instruction as uninterruptible: there is some special case logic to
// allow this jump to execute without flushing the final stack adjust uop, which can
// cause the wrong exception PC to be sampled if this uop is interrupted.
uop_atomic = 1'b1;
in_uop_seq = 1'b1;
uop_ctr_nxt = uop_ctr + 4'h1;
instr_out = `RVOPC_NOZ_JALR | rfmt_rs1(5'h1);
end else if (uop_ctr == 4'hf) begin
in_uop_seq = 1'b1;
uop_seq_end = 1'b1;
uop_atomic = 1'b1;
uop_ctr_nxt = 4'h0;
uop_no_pc_update = 1'b1;
instr_out = zcmp_pop_stack_adj_instr;
@ -371,13 +363,10 @@ end else begin: instr_decompress
instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(5'd10); // li a0, 0
end else if (uop_ctr == 4'he) begin
in_uop_seq = 1'b1;
uop_atomic = 1'b1;
uop_ctr_nxt = uop_ctr + 4'h1;
instr_out = `RVOPC_NOZ_JALR | rfmt_rs1(5'h1);
end else if (uop_ctr == 4'hf) begin
in_uop_seq = 1'b1;
uop_seq_end = 1'b1;
uop_atomic = 1'b1;
uop_ctr_nxt = 4'h0;
uop_no_pc_update = 1'b1;
instr_out = zcmp_pop_stack_adj_instr;
@ -400,8 +389,6 @@ end else begin: instr_decompress
instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(zcmp_sa01_r1s) | rfmt_rs1(5'd10);
end else begin
in_uop_seq = 1'b1;
uop_seq_end = 1'b1;
uop_atomic = 1'b1;
uop_ctr_nxt = 4'h0;
instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(zcmp_sa01_r2s) | rfmt_rs1(5'd11);
end
@ -415,8 +402,6 @@ end else begin: instr_decompress
instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(5'd10) | rfmt_rs1(zcmp_sa01_r1s);
end else begin
in_uop_seq = 1'b1;
uop_seq_end = 1'b1;
uop_atomic = 1'b1;
uop_ctr_nxt = 4'h0;
instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(5'd11) | rfmt_rs1(zcmp_sa01_r2s);
end
@ -442,7 +427,10 @@ if (EXTENSION_ZCMP) begin: have_uop_ctr;
end else begin
uop_ctr <= uop_ctr_nxt;
`ifdef HAZARD3_ASSERTIONS
assert(uop_ctr == 4'h0 || in_uop_seq);
assert(in_uop_seq || uop_ctr == 4'h0);
assert(in_uop_seq || zcmp_ls_reg == 5'h01);
assert(in_uop_seq || !uop_atomic);
assert(in_uop_seq || !uop_no_pc_update);
if (uop_seq_end) begin
assert(in_uop_seq);
assert(instr_out_uop_stall || uop_ctr_nxt == 4'h0);