Luke Wren a18c3018e1 Bump riscv-formal to head of hazard3 branch, not sure what happened there		2022-10-07 01:35:10 +01:00
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riscv-formal@c12efe293f	Bump riscv-formal to head of hazard3 branch, not sure what happened there	2022-10-07 01:35:10 +01:00
tb	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00