Luke Wren 0199f48087 Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented		2022-05-24 16:44:03 +01:00
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formal	RVFI monitor: blank out instructions which experienced an instruction fetch fault.	2022-04-12 13:38:19 +01:00
sim	Add read-only counter CSRs to readability/writability tests, and fix cycleh being unreadable when U mode is not implemented	2022-05-24 16:44:03 +01:00
.gitignore	Import from hazard5 9743a1b	2021-05-21 02:34:16 +01:00