Luke Wren ad5fd24772 - Fix signal named priority, which is a keyword in SV ... - Fix incorrect HIGHEST_WINS behaviour in one-hot selector - Add test for asserting 32 IRQs at 16 priorities at once - Add an entry counter to the soft dispatch code so tests can check the number of times hardware entered the vector		2022-08-07 23:17:03 +01:00
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hazard3_alu.v	First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)	2022-08-07 20:51:12 +01:00
hazard3_branchcmp.v	Perf option for dedicated branch comparator	2022-04-02 11:40:47 +01:00
hazard3_mul_fast.v	Add MUL_FASTER option to retire fast mul to stage 2 instead of stage 3	2022-07-05 03:37:19 +01:00
hazard3_muldiv_seq.v	Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,	2022-06-25 20:08:40 +01:00
hazard3_onehot_encode.v	First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)	2022-08-07 20:51:12 +01:00
hazard3_onehot_priority.v	- Fix signal named priority, which is a keyword in SV	2022-08-07 23:17:03 +01:00
hazard3_onehot_priority_dynamic.v	- Fix signal named priority, which is a keyword in SV	2022-08-07 23:17:03 +01:00
hazard3_priority_encode.v	First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)	2022-08-07 20:51:12 +01:00
hazard3_shift_barrel.v	Add separate define HAZARD3_ASSERTIONS for enabling internal assertions,	2022-06-25 20:08:40 +01:00
muldiv_model.py	Import from hazard5 9743a1b	2021-05-21 02:34:16 +01:00