Luke Wren b1225c386c Add missing 1port SBA change, and update example soc and bus compliance tb to reflect		2022-07-03 17:57:03 +01:00
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example_soc.v	Add missing 1port SBA change, and update example soc and bus compliance tb to reflect	2022-07-03 17:57:03 +01:00
soc.f	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00