Luke Wren f48177c644 Tie off debug LEDs in ULX3S top level		2022-09-05 00:37:44 +01:00
..
fpga	Tie off debug LEDs in ULX3S top level	2022-09-05 00:37:44 +01:00
libfpga@9d50e12e01	Bump libfpga for correct bus error response from AHBL splitter in example SoC	2021-11-28 01:35:52 +00:00
soc	Example soc: connect up power signals and always-on clock. Set more parameters explicitly.	2022-09-04 23:42:48 +01:00
synth	Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker	2021-11-21 15:55:52 +00:00
icebreaker-openocd.cfg	Small code cleanup	2021-07-24 10:08:27 +01:00
ulx3s-openocd.cfg	Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.	2021-07-23 18:32:47 +01:00