Hazard3/test/sim/tb_cxxrtl
Luke Wren c1f17b0b23 Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench 2021-11-06 09:59:27 +00:00
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.gitignore Organise test directory into formal and sim 2021-05-23 07:42:35 +01:00
Makefile Just use read_verilog; write_cxxrtl when building tb_cxxrtl 2021-07-22 17:30:30 +01:00
tb.cpp Add wfi timer loop example, and add mtime/mtimecmp to non-debug testbench 2021-11-06 09:59:27 +00:00