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Hazard3/test/sim/common
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Luke Wren 15cb21ae43 First pass at implementing the new IRQ controls. Works well enough that the old tests pass :) 2022-08-07 20:51:12 +01:00
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hazard3_csr.h First pass at implementing the new IRQ controls. Works well enough that the old tests pass :) 2022-08-07 20:51:12 +01:00
hazard3_irq.h First pass at implementing the new IRQ controls. Works well enough that the old tests pass :) 2022-08-07 20:51:12 +01:00
init.S Add exclusives monitor to testbench 2021-12-17 17:03:35 +00:00
memmap.ld Add RISC-V debug tests 2021-07-22 17:50:04 +01:00
src_only_app.mk Consolidate openocd and bin-load testbenches 2021-12-11 09:46:38 +00:00
tb_cxxrtl_io.h Add exclusives monitor to testbench 2021-12-17 17:03:35 +00:00