194 lines
8.9 KiB
C
194 lines
8.9 KiB
C
#include "tb_cxxrtl_io.h"
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#include "hazard3_csr.h"
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// Check all implemented M-mode CSRs generate exceptions when written, *if and
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// only if* they are read-only.
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// These are new (priv-1.12) and may not be recognised by the toolchain:
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#define mconfigptr 0xf15
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#define mstatush 0x310
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// Explanations in inline comments within the expected output:
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/*EXPECTED-OUTPUT***************************************************************
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-> exception, mcause = 2 // write to mvendorid, read-only
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CSR was f11
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-> exception, mcause = 2 // write to marchid, read-only
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CSR was f12
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-> exception, mcause = 2 // write to mimpid, read-only
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CSR was f13
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-> exception, mcause = 2 // write to mhartid, read-only
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CSR was f14
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-> exception, mcause = 2 // write to mconfigptr, read-only
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CSR was f15
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-> exception, mcause = 2 // read of medeleg, unimplemented
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CSR was 302
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-> exception, mcause = 2 // write to medegeleg, unimplemented
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CSR was 302
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-> exception, mcause = 2 // read of mideleg, unimplemented
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CSR was 303
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-> exception, mcause = 2 // write to medeleg, unimplemented
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CSR was 303
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-> exception, mcause = 2 // write to cycle, read-only
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CSR was c00
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-> exception, mcause = 2 // write to cycleh, read-only
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CSR was c80
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-> exception, mcause = 2 // write to instret, read-only
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CSR was c02
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-> exception, mcause = 2 // write to instreth, read-only
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CSR was c82
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-> exception, mcause = 2 // write to tselect, unimplemented but we permit reads as a workaround for an OpenOCD bug
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CSR was 7a0
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-> exception, mcause = 2 // read of tdata1, unimplemented
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CSR was 7a1
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-> exception, mcause = 2 // write to tdata1, unimplemented
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CSR was 7a1
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-> exception, mcause = 2 // read of dcsr, D-mode
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CSR was 7b0
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-> exception, mcause = 2 // write to dcsr, D-mode
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CSR was 7b0
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-> exception, mcause = 2 // read of dpc, D-mode
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CSR was 7b1
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-> exception, mcause = 2 // write to dpc, D-mode
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CSR was 7b1
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-> exception, mcause = 2 // read of dscratch0, unimplemented, D-mode
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CSR was 7b2
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-> exception, mcause = 2 // write to dscratch0, unimplemented, D-mode
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CSR was 7b2
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-> exception, mcause = 2 // read of dscratch1, unimplemented, D-mode
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CSR was 7b3
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-> exception, mcause = 2 // write to dscratch1, unimplemented, D-mode
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CSR was 7b3
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-> exception, mcause = 2 // read of dmdata0, D-mode
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CSR was bff
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-> exception, mcause = 2 // write to dmdata0, D-mode
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CSR was bff
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*******************************************************************************/
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int main() {
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write_csr(mvendorid, read_csr(mvendorid ));
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write_csr(marchid, read_csr(marchid ));
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write_csr(mimpid, read_csr(mimpid ));
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write_csr(mhartid, read_csr(mhartid ));
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write_csr(mconfigptr, read_csr(mconfigptr ));
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write_csr(misa, read_csr(misa ));
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write_csr(mstatus, read_csr(mstatus ));
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write_csr(mstatush, read_csr(mstatush ));
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write_csr(medeleg, read_csr(medeleg ));
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write_csr(mideleg, read_csr(mideleg ));
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write_csr(mie, read_csr(mie ));
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write_csr(mip, read_csr(mip ));
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write_csr(mtvec, read_csr(mtvec ));
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write_csr(mscratch, read_csr(mscratch ));
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write_csr(mepc, read_csr(mepc ));
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write_csr(mcause, read_csr(mcause ));
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write_csr(mtval, read_csr(mtval ));
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write_csr(mcycle, read_csr(mcycle ));
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write_csr(mcycleh, read_csr(mcycleh ));
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write_csr(minstret, read_csr(minstret ));
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write_csr(minstreth, read_csr(minstreth ));
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write_csr(mhpmcounter3, read_csr(mhpmcounter3 ));
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write_csr(mhpmcounter4, read_csr(mhpmcounter4 ));
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write_csr(mhpmcounter5, read_csr(mhpmcounter5 ));
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write_csr(mhpmcounter6, read_csr(mhpmcounter6 ));
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write_csr(mhpmcounter7, read_csr(mhpmcounter7 ));
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write_csr(mhpmcounter8, read_csr(mhpmcounter8 ));
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write_csr(mhpmcounter9, read_csr(mhpmcounter9 ));
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write_csr(mhpmcounter10, read_csr(mhpmcounter10 ));
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write_csr(mhpmcounter11, read_csr(mhpmcounter11 ));
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write_csr(mhpmcounter12, read_csr(mhpmcounter12 ));
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write_csr(mhpmcounter13, read_csr(mhpmcounter13 ));
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write_csr(mhpmcounter14, read_csr(mhpmcounter14 ));
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write_csr(mhpmcounter15, read_csr(mhpmcounter15 ));
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write_csr(mhpmcounter16, read_csr(mhpmcounter16 ));
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write_csr(mhpmcounter17, read_csr(mhpmcounter17 ));
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write_csr(mhpmcounter18, read_csr(mhpmcounter18 ));
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write_csr(mhpmcounter19, read_csr(mhpmcounter19 ));
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write_csr(mhpmcounter20, read_csr(mhpmcounter20 ));
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write_csr(mhpmcounter21, read_csr(mhpmcounter21 ));
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write_csr(mhpmcounter22, read_csr(mhpmcounter22 ));
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write_csr(mhpmcounter23, read_csr(mhpmcounter23 ));
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write_csr(mhpmcounter24, read_csr(mhpmcounter24 ));
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write_csr(mhpmcounter25, read_csr(mhpmcounter25 ));
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write_csr(mhpmcounter26, read_csr(mhpmcounter26 ));
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write_csr(mhpmcounter27, read_csr(mhpmcounter27 ));
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write_csr(mhpmcounter28, read_csr(mhpmcounter28 ));
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write_csr(mhpmcounter29, read_csr(mhpmcounter29 ));
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write_csr(mhpmcounter30, read_csr(mhpmcounter30 ));
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write_csr(mhpmcounter31, read_csr(mhpmcounter31 ));
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write_csr(mhpmcounter3h, read_csr(mhpmcounter3h ));
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write_csr(mhpmcounter4h, read_csr(mhpmcounter4h ));
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write_csr(mhpmcounter5h, read_csr(mhpmcounter5h ));
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write_csr(mhpmcounter6h, read_csr(mhpmcounter6h ));
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write_csr(mhpmcounter7h, read_csr(mhpmcounter7h ));
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write_csr(mhpmcounter8h, read_csr(mhpmcounter8h ));
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write_csr(mhpmcounter9h, read_csr(mhpmcounter9h ));
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write_csr(mhpmcounter10h, read_csr(mhpmcounter10h ));
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write_csr(mhpmcounter11h, read_csr(mhpmcounter11h ));
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write_csr(mhpmcounter12h, read_csr(mhpmcounter12h ));
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write_csr(mhpmcounter13h, read_csr(mhpmcounter13h ));
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write_csr(mhpmcounter14h, read_csr(mhpmcounter14h ));
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write_csr(mhpmcounter15h, read_csr(mhpmcounter15h ));
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write_csr(mhpmcounter16h, read_csr(mhpmcounter16h ));
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write_csr(mhpmcounter17h, read_csr(mhpmcounter17h ));
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write_csr(mhpmcounter18h, read_csr(mhpmcounter18h ));
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write_csr(mhpmcounter19h, read_csr(mhpmcounter19h ));
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write_csr(mhpmcounter20h, read_csr(mhpmcounter20h ));
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write_csr(mhpmcounter21h, read_csr(mhpmcounter21h ));
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write_csr(mhpmcounter22h, read_csr(mhpmcounter22h ));
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write_csr(mhpmcounter23h, read_csr(mhpmcounter23h ));
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write_csr(mhpmcounter24h, read_csr(mhpmcounter24h ));
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write_csr(mhpmcounter25h, read_csr(mhpmcounter25h ));
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write_csr(mhpmcounter26h, read_csr(mhpmcounter26h ));
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write_csr(mhpmcounter27h, read_csr(mhpmcounter27h ));
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write_csr(mhpmcounter28h, read_csr(mhpmcounter28h ));
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write_csr(mhpmcounter29h, read_csr(mhpmcounter29h ));
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write_csr(mhpmcounter30h, read_csr(mhpmcounter30h ));
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write_csr(mhpmcounter31h, read_csr(mhpmcounter31h ));
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write_csr(cycle, read_csr(cycle ));
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write_csr(cycleh, read_csr(cycleh ));
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write_csr(instret, read_csr(instret ));
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write_csr(instreth, read_csr(instreth ));
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write_csr(mcountinhibit, read_csr(mcountinhibit ));
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write_csr(mhpmevent3, read_csr(mhpmevent3 ));
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write_csr(tselect, read_csr(tselect ));
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write_csr(tdata1, read_csr(tdata1 ));
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write_csr(dcsr, read_csr(dcsr ));
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write_csr(dpc, read_csr(dpc ));
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write_csr(dscratch0, read_csr(dscratch0 ));
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write_csr(dscratch1, read_csr(dscratch1 ));
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write_csr(hazard3_csr_dmdata0, read_csr(hazard3_csr_dmdata0));
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write_csr(hazard3_csr_meiea, read_csr(hazard3_csr_meiea ));
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write_csr(hazard3_csr_meipa, read_csr(hazard3_csr_meipa ));
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write_csr(hazard3_csr_meifa, read_csr(hazard3_csr_meifa ));
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write_csr(hazard3_csr_meipr, read_csr(hazard3_csr_meipr ));
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write_csr(hazard3_csr_meinext, read_csr(hazard3_csr_meinext ));
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write_csr(hazard3_csr_meicontext, read_csr(hazard3_csr_meicontext));
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return 0;
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}
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void __attribute__((interrupt)) handle_exception() {
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tb_printf("-> exception, mcause = %u\n", read_csr(mcause));
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write_csr(mcause, 0);
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uint32_t mepc = read_csr(mepc);
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if ((*(uint16_t*)mepc & 0x3) == 0x3) {
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tb_printf("CSR was %03x\n", *(uint16_t*)(mepc + 2) >> 4);
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mepc += 4;
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}
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else {
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tb_puts("Exception on 16-bit instruction?!\n");
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tb_exit(-1);
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}
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write_csr(mepc, mepc);
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}
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