Luke Wren 15cb21ae43 First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)		2022-08-07 20:51:12 +01:00
..
.gitignore	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
Makefile	First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)	2022-08-07 20:51:12 +01:00
compliance.cfg	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
gdbinit	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
multicore-openocd.cfg	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
multicore.gtkw	Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench)	2022-07-06 23:53:11 +01:00
openocd.cfg	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
tb.cpp	Add testbench flag to propagate CPU return code to testbench return	2022-05-28 15:00:28 +01:00
tb.f	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
tb.v	First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)	2022-08-07 20:51:12 +01:00
tb_common.f	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
tb_multicore.f	Add multicore tb integration file	2021-12-17 00:41:23 +00:00
tb_multicore.v	First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)	2022-08-07 20:51:12 +01:00
waves.gtkw	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00