290 lines
8.6 KiB
C++
290 lines
8.6 KiB
C++
#include "rv_csr.h"
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#include "encoding/rv_csr.h"
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#include <cassert>
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#include <cstdio>
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// Inclusive msb:lsb style, like Verilog (and like the ISA manual)
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#define BITS_UPTO(msb) (~((-1u << (msb)) << 1))
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#define BITRANGE(msb, lsb) (BITS_UPTO((msb) - (lsb)) << (lsb))
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#define GETBITS(x, msb, lsb) (((x) & BITRANGE(msb, lsb)) >> (lsb))
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#define GETBIT(x, bit) (((x) >> (bit)) & 1u)
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ux_t RVCSR::get_effective_xip() {
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return mip |
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(irq_s ? MIP_MSIP : 0) |
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(irq_t ? MIP_MTIP : 0) |
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(irq_e ? MIP_MEIP : 0);
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}
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void RVCSR::step() {
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uint64_t mcycle_64 = ((uint64_t)mcycleh << 32) | mcycle;
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uint64_t minstret_64 = ((uint64_t)minstreth << 32) | minstret;
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if (!(mcountinhibit & 0x1u)) {
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++mcycle_64;
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}
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if (!(mcountinhibit & 0x4u)) {
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++minstret_64;
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}
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if (!(pending_write_addr && *pending_write_addr == CSR_MCYCLEH)) {
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mcycleh = mcycle_64 >> 32;
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}
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if (!(pending_write_addr && *pending_write_addr == CSR_MCYCLE)) {
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mcycle = mcycle_64 & 0xffffffffu;
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}
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if (!(pending_write_addr && *pending_write_addr == CSR_MINSTRETH)) {
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minstreth = minstret_64 >> 32;
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}
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if (!(pending_write_addr && *pending_write_addr == CSR_MINSTRET)) {
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minstret = minstret_64 & 0xffffffffu;
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}
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if (pending_write_addr) {
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switch (*pending_write_addr) {
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case CSR_MSTATUS: mstatus = pending_write_data; break;
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case CSR_MIE: mie = pending_write_data; break;
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case CSR_MTVEC: mtvec = pending_write_data & 0xfffffffdu; break;
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case CSR_MSCRATCH: mscratch = pending_write_data; break;
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case CSR_MEPC: mepc = pending_write_data & 0xfffffffeu; break;
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case CSR_MCAUSE: mcause = pending_write_data & 0x8000000fu; break;
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case CSR_MCYCLE: mcycle = pending_write_data; break;
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case CSR_MCYCLEH: mcycleh = pending_write_data; break;
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case CSR_MINSTRET: minstret = pending_write_data; break;
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case CSR_MINSTRETH: minstreth = pending_write_data; break;
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case CSR_MCOUNTINHIBIT: mcountinhibit = pending_write_data & 0x7u; break;
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default: break;
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}
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for (uint i = 0; i < IMPLEMENTED_PMP_REGIONS; ++i) {
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if (pmpcfg_l(i)) {
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continue;
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}
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if (*pending_write_addr == CSR_PMPADDR0 + i) {
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pmpaddr[i] = pending_write_data & 0x3fffffffu;
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} else if (*pending_write_addr == CSR_PMPCFG0 + i / 4) {
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uint field_lsb = 8 * (i % 4);
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pmpcfg[i / 4] = (pmpcfg[i / 4] & ~(0xffu << field_lsb))
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| (pending_write_data & (0x9fu << field_lsb));
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}
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}
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pending_write_addr = {};
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}
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}
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// Returns None on permission/decode fail
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std::optional<ux_t> RVCSR::read(uint16_t addr, bool side_effect) {
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if (addr >= 1u << 12 || GETBITS(addr, 9, 8) > priv)
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return {};
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switch (addr) {
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case CSR_MISA: return 0x40901105; // RV32IMACX + U
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case CSR_MHARTID: return 0;
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case CSR_MARCHID: return 0x1b; // Hazard3
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case CSR_MIMPID: return 0x12345678u; // Match testbench value
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case CSR_MVENDORID: return 0xdeadbeefu; // Match testbench value
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case CSR_MCONFIGPTR: return 0x9abcdef0u; // Match testbench value
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case CSR_MSTATUS: return mstatus;
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case CSR_MIE: return mie;
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case CSR_MIP: return get_effective_xip();
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case CSR_MTVEC: return mtvec;
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case CSR_MSCRATCH: return mscratch;
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case CSR_MEPC: return mepc;
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case CSR_MCAUSE: return mcause;
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case CSR_MTVAL: return 0;
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case CSR_MCOUNTINHIBIT: return mcountinhibit;
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case CSR_MCYCLE: return mcycle;
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case CSR_MCYCLEH: return mcycleh;
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case CSR_MINSTRET: return minstret;
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case CSR_MINSTRETH: return minstreth;
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case CSR_PMPCFG0: return pmpcfg[0];
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case CSR_PMPCFG1: return pmpcfg[1];
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case CSR_PMPCFG2: return pmpcfg[2];
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case CSR_PMPCFG3: return pmpcfg[3];
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case CSR_PMPADDR0: return pmpaddr[0];
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case CSR_PMPADDR1: return pmpaddr[1];
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case CSR_PMPADDR2: return pmpaddr[2];
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case CSR_PMPADDR3: return pmpaddr[3];
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case CSR_PMPADDR4: return pmpaddr[4];
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case CSR_PMPADDR5: return pmpaddr[5];
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case CSR_PMPADDR6: return pmpaddr[6];
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case CSR_PMPADDR7: return pmpaddr[7];
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case CSR_PMPADDR8: return pmpaddr[8];
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case CSR_PMPADDR9: return pmpaddr[9];
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case CSR_PMPADDR10: return pmpaddr[10];
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case CSR_PMPADDR11: return pmpaddr[11];
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case CSR_PMPADDR12: return pmpaddr[12];
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case CSR_PMPADDR13: return pmpaddr[13];
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case CSR_PMPADDR14: return pmpaddr[14];
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case CSR_PMPADDR15: return pmpaddr[15];
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default: return {};
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}
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}
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// Returns false on permission/decode fail
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bool RVCSR::write(uint16_t addr, ux_t data, uint op) {
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if (addr >= 1u << 12 || GETBITS(addr, 9, 8) > priv)
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return false;
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if (op == WRITE_CLEAR || op == WRITE_SET) {
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std::optional<ux_t> rdata = read(addr, false);
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if (!rdata)
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return false;
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if (op == WRITE_CLEAR)
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data = *rdata & ~data;
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else
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data = *rdata | data;
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}
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pending_write_addr = addr;
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pending_write_data = data;
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// Actual write is applied at end of step() -- ordering is important
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// e.g. for mcycle updates. However we validate address for
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// writability immediately.
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switch (addr) {
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case CSR_MISA: break;
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case CSR_MHARTID: break;
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case CSR_MARCHID: break;
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case CSR_MIMPID: break;
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case CSR_MSTATUS: break;
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case CSR_MIE: break;
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case CSR_MIP: break;
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case CSR_MTVEC: break;
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case CSR_MSCRATCH: break;
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case CSR_MEPC: break;
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case CSR_MCAUSE: break;
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case CSR_MTVAL: break;
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case CSR_MCYCLE: break;
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case CSR_MCYCLEH: break;
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case CSR_MINSTRET: break;
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case CSR_MINSTRETH: break;
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case CSR_MCOUNTINHIBIT: break;
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case CSR_PMPCFG0: break;
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case CSR_PMPCFG1: break;
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case CSR_PMPCFG2: break;
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case CSR_PMPCFG3: break;
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case CSR_PMPADDR0: break;
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case CSR_PMPADDR1: break;
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case CSR_PMPADDR2: break;
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case CSR_PMPADDR3: break;
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case CSR_PMPADDR4: break;
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case CSR_PMPADDR5: break;
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case CSR_PMPADDR6: break;
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case CSR_PMPADDR7: break;
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case CSR_PMPADDR8: break;
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case CSR_PMPADDR9: break;
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case CSR_PMPADDR10: break;
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case CSR_PMPADDR11: break;
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case CSR_PMPADDR12: break;
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case CSR_PMPADDR13: break;
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case CSR_PMPADDR14: break;
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case CSR_PMPADDR15: break;
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default: return false;
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}
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return true;
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}
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ux_t RVCSR::trap_enter_exception(uint xcause, ux_t xepc) {
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assert(xcause < 32);
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assert(!pending_write_addr);
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return trap_enter(xcause, xepc);
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}
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std::optional<ux_t> RVCSR::trap_check_enter_irq(ux_t xepc) {
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ux_t m_targeted_irqs = get_effective_xip() & mie;
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bool take_m_irq = m_targeted_irqs && ((mstatus & MSTATUS_MIE) || priv < PRV_M);
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if (take_m_irq) {
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ux_t cause = (1u << 31) | __builtin_ctz(m_targeted_irqs);
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return trap_enter(cause, xepc);
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} else {
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return std::nullopt;
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}
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}
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// Update trap state (including change of privilege level), return trap target PC
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ux_t RVCSR::trap_enter(uint xcause, ux_t xepc) {
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mstatus = (mstatus & ~MSTATUS_MPP) | (priv << 11);
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priv = PRV_M;
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if (mstatus & MSTATUS_MIE)
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mstatus |= MSTATUS_MPIE;
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mstatus &= ~MSTATUS_MIE;
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mcause = xcause;
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mepc = xepc;
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if ((mtvec & 0x1) && (xcause & (1u << 31))) {
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return (mtvec & -2) + 4 * (xcause & ~(1u << 31));
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} else {
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return mtvec & -2;
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}
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}
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// Update trap state, return mepc:
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ux_t RVCSR::trap_mret() {
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priv = GETBITS(mstatus, 12, 11);
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mstatus &= ~MSTATUS_MPP;
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if (priv != PRV_M)
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mstatus &= ~MSTATUS_MPRV;
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if (mstatus & MSTATUS_MPIE)
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mstatus |= MSTATUS_MIE;
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mstatus &= ~MSTATUS_MPIE;
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return mepc;
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}
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int RVCSR::get_pmp_match(ux_t addr) {
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for (int i = 0; i < PMP_REGIONS; ++i) {
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if (pmpcfg_a(i) == 0u) {
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continue;
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}
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ux_t mask = 0xffffffffu;
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if (pmpcfg_a(i) == 3) {
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if (pmpaddr[i] == 0xffffffffu) {
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mask = 0u;
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} else {
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mask = 0xfffffffeu << __builtin_ctz(~pmpaddr[i]);
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}
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}
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bool match = ((addr >> 2) & mask) == (pmpaddr[i] & mask);
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if (match) {
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// Lowest-numbered match determines success/failure:
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return i;
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}
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}
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return -1;
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}
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uint RVCSR::get_pmp_xwr(ux_t addr) {
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int region = get_pmp_match(addr);
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bool match = false;
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uint matching_xwr = 0;
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uint matching_l = 0;
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if (region >= 0) {
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match = true;
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matching_xwr = pmpcfg_xwr(region);
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matching_l = pmpcfg_l(region);
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}
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if (match) {
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// TODO MPRV
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if (get_true_priv() == PRV_M && !matching_l) {
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return 0x7u;
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} else {
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return matching_xwr;
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}
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} else {
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return get_true_priv() == PRV_M ? 0x7u : 0x0u;
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}
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}
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