137 lines
3.6 KiB
Verilog
137 lines
3.6 KiB
Verilog
module rvfi_wrapper (
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input wire clock,
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input wire reset,
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`RVFI_OUTPUTS
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);
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// ----------------------------------------------------------------------------
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// Memory Interface
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// ----------------------------------------------------------------------------
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(* keep *) wire [31:0] i_haddr;
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(* keep *) wire i_hwrite;
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(* keep *) wire [1:0] i_htrans;
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(* keep *) wire [2:0] i_hsize;
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(* keep *) wire [2:0] i_hburst;
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(* keep *) wire [3:0] i_hprot;
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(* keep *) wire i_hmastlock;
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(* keep *) `rvformal_rand_reg i_hready;
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(* keep *) `rvformal_rand_reg i_hresp;
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(* keep *) wire [31:0] i_hwdata;
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(* keep *) `rvformal_rand_reg [31:0] i_hrdata;
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(* keep *) wire [31:0] d_haddr;
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(* keep *) wire d_hwrite;
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(* keep *) wire [1:0] d_htrans;
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(* keep *) wire [2:0] d_hsize;
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(* keep *) wire [2:0] d_hburst;
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(* keep *) wire [3:0] d_hprot;
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(* keep *) wire d_hmastlock;
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(* keep *) `rvformal_rand_reg d_hready;
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(* keep *) `rvformal_rand_reg d_hresp;
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(* keep *) wire [31:0] d_hwdata;
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(* keep *) `rvformal_rand_reg [31:0] d_hrdata;
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`ifdef RISCV_FORMAL_FAIRNESS
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localparam MAX_BUS_STALL = 8;
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`else
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localparam MAX_BUS_STALL = -1;
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`endif
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ahbl_slave_assumptions #(
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.MAX_BUS_STALL (MAX_BUS_STALL)
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) i_slave_assumptions (
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.clk (clock),
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.rst_n (!reset),
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.dst_hready_resp (i_hready),
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.dst_hready (i_hready),
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.dst_hresp (i_hresp),
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.dst_haddr (i_haddr),
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.dst_hwrite (i_hwrite),
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.dst_htrans (i_htrans),
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.dst_hsize (i_hsize),
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.dst_hburst (i_hburst),
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.dst_hprot (i_hprot),
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.dst_hmastlock (i_hmastlock),
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.dst_hwdata (i_hwdata),
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.dst_hrdata (i_hrdata)
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);
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ahbl_slave_assumptions #(
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.MAX_BUS_STALL (MAX_BUS_STALL)
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) d_slave_assumptions (
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.clk (clock),
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.rst_n (!reset),
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.dst_hready_resp (d_hready),
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.dst_hready (d_hready),
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.dst_hresp (d_hresp),
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.dst_haddr (d_haddr),
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.dst_hwrite (d_hwrite),
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.dst_htrans (d_htrans),
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.dst_hsize (d_hsize),
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.dst_hburst (d_hburst),
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.dst_hprot (d_hprot),
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.dst_hmastlock (d_hmastlock),
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.dst_hwdata (d_hwdata),
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.dst_hrdata (d_hrdata)
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);
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// ----------------------------------------------------------------------------
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// Device Under Test
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// ----------------------------------------------------------------------------
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// FIXME IRQs are tied off because riscv-formal doesn't accept the
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// nonsequential pc_wdata when an instruction is followed by an interrupt
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// (and the rvfi_intr signal doesn't do anything)
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wire [15:0] irq = 0;
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// (* keep *) `rvformal_rand_reg [15:0] irq;
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hazard3_cpu_2port #(
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.RESET_VECTOR (0),
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.EXTENSION_C (1),
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.EXTENSION_M (1),
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.MUL_FAST (1),
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.MULDIV_UNROLL (2)
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) dut (
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.clk (clock),
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.rst_n (!reset),
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.i_haddr (i_haddr),
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.i_hwrite (i_hwrite),
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.i_htrans (i_htrans),
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.i_hsize (i_hsize),
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.i_hburst (i_hburst),
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.i_hprot (i_hprot),
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.i_hmastlock (i_hmastlock),
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.i_hready (i_hready),
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.i_hresp (i_hresp),
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.i_hwdata (i_hwdata),
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.i_hrdata (i_hrdata),
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.d_haddr (d_haddr),
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.d_hwrite (d_hwrite),
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.d_htrans (d_htrans),
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.d_hsize (d_hsize),
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.d_hburst (d_hburst),
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.d_hprot (d_hprot),
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.d_hmastlock (d_hmastlock),
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.d_hready (d_hready),
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.d_hresp (d_hresp),
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.d_hwdata (d_hwdata),
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.d_hrdata (d_hrdata),
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.irq (irq),
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`RVFI_CONN
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);
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endmodule
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