Luke Wren e68d8a6cd6 Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.		2022-06-13 01:23:32 +01:00
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csr.adoc	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00
debug.adoc	More docs cleanup	2021-12-02 02:29:34 +00:00
instruction_timings.adoc	Fix cycle timing docs for sc.w: 2 cycles if next instruction is RAW-dependent.	2021-12-12 20:50:26 +00:00
introduction.adoc	Add A bit to MISA, update docs	2021-12-07 05:10:20 +00:00