112 lines
3.2 KiB
C
112 lines
3.2 KiB
C
#include "tb_cxxrtl_io.h"
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#include "hazard3_csr.h"
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#include "pmp.h"
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// Check MPRV is cleared when returning to U mode, but not when returning to M
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// mode. Check that mret clears MPP, no matter which mode is returned to.
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/*EXPECTED-OUTPUT***************************************************************
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Enabling MPRV, with MPP=M
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mret to M, check MPRV
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mstatus = 00020080 // mprv=1 mpp=U mpie=1
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mret to M, check MPP affects load/store
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mcause = 7 // store fault
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mstatus = 00021880 // mprv=1 mpp=M mpie=1
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mem[mepc] = c108
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mret to U, check MPRV
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mcause = 1 // instr access fault
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mstatus = 00000080 // mprv=0 mpp=U mpie=1
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mem[mepc] = 0001 // c.nop
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*******************************************************************************/
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volatile uint32_t scratch_word;
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#define MPRV (1u << 17)
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#define MPP (3u << 11)
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extern void handle_exception();
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int main() {
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// Leave PMP in default state (no U permissions).
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scratch_word = 0;
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tb_puts("Enabling MPRV, with MPP=M\n");
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set_csr(mstatus, MPP | MPRV);
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// Check that mret to M does not clear MPRV (also, opportunistically,
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// check that mret to M clears MPP)
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tb_puts("mret to M, check MPRV\n");
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write_csr(mtvec, (uintptr_t)&handle_exception);
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uint32_t mstatus_check;
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asm volatile (
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"la %0, 1f\n"
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"csrw mepc, %0\n"
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"mret\n"
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".p2align 2\n"
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"1:\n"
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// Note MPP is cleared by the MRET, so must be re-set immediately so
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// we can do load/stores again. We read out the current mstatus value
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// at the same time we modify it.
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"li %0, 0x1800\n"
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"csrrs %0, mstatus, %0\n"
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: "+r" (mstatus_check)
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);
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// MPP should be U. MPRV should still be set.
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tb_printf("mstatus = %08x\n", mstatus_check);
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// The actual value of MPP is now M again, since we fixed it up.
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// Check that clearing of MPP upon mret immediately affects the
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// MPRV-modified load/store privilege level.
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tb_puts("mret to M, check MPP affects load/store\n");
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write_csr(mcause, 0);
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asm (
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"la a0, 1f\n"
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"csrw mepc, a0\n"
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"la a0, 2f\n"
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"csrw mtvec, a0\n"
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"la a0, scratch_word\n"
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"mret\n"
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".p2align 2\n"
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"1:\n"
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// We just executed a return from M mode to M mode, but our MPP was
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// cleared in the process, and our MPRV should still be set.
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// Therefore our effective load/store privilege is U:
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"c.sw a0, (a0)\n"
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// Catch the trap we just caused, and restore MPP to M.
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".p2align 2\n"
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"2:\n"
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"li a0, 0x1800\n"
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"csrs mstatus, a0\n"
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: : : "a0"
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);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_printf("mstatus = %08x\n", read_csr(mstatus));
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tb_printf("mem[mepc] = %04x\n", *(uint16_t*)read_csr(mepc));
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// Check that mret to U (followed by trapping back to M, as we can't
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// actually check MPRV from U) *does* clear MPRV
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tb_puts("mret to U, check MPRV\n");
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asm (
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"la a0, 1f\n"
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"csrw mepc, a0\n"
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"csrw mtvec, a0\n"
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"li a0, 0x1800\n"
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"csrc mstatus, a0\n"
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"mret\n"
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".p2align 2\n"
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// We execute this address twice, first in U-mode then in M-mode:
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"1:\n"
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"c.nop\n"
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: : : "a0"
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);
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tb_printf("mcause = %u\n", read_csr(mcause));
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tb_printf("mstatus = %08x\n", read_csr(mstatus));
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tb_printf("mem[mepc] = %04x\n", *(uint16_t*)read_csr(mepc));
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tb_assert(read_csr(mepc) == read_csr(mtvec), "Should trap to same address that trapped\n");
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return 0;
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}
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