Luke Wren 31efd07042 Fix incorrect tracking of predictedness of fetch data phase. Fixes performance regression in RV32IMC CoreMark (now runs faster, as it should.)		2022-06-25 11:32:56 +01:00
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arith	Update copyright years	2022-06-09 00:12:01 +01:00
debug	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3.f	Integrate PMP, and fix a couple of PMP bugs	2022-05-24 19:57:45 +01:00
hazard3_config.vh	First pass at adding branch prediction	2022-06-15 02:05:46 +01:00
hazard3_config_inst.vh	First pass at adding branch prediction	2022-06-15 02:05:46 +01:00
hazard3_core.v	Attempt to fix fetch mismatch caused by jumping halfway into a 32-bit	2022-06-24 19:58:21 +01:00
hazard3_cpu_1port.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_cpu_2port.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_csr.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_csr_addr.vh	First pass at U-mode CSR support. Bizarrely causes CXXRTL tb to not write to stdout when invoked by subprocess.run from Python.	2022-05-24 16:17:54 +01:00
hazard3_decode.v	Fix incorrect tracking of predictedness of fetch data phase. Fixes performance regression in RV32IMC CoreMark (now runs faster, as it should.)	2022-06-25 11:32:56 +01:00
hazard3_frontend.v	Fix incorrect tracking of predictedness of fetch data phase. Fixes performance regression in RV32IMC CoreMark (now runs faster, as it should.)	2022-06-25 11:32:56 +01:00
hazard3_instr_decompress.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_ops.vh	ecall from U-mode has a different mcause value than ecall from M-mode	2022-05-28 12:07:29 +01:00
hazard3_pmp.v	PMP config: separate granularity config from hardwired region config. Give correct read value for G > 1.	2022-06-03 17:09:43 +01:00
hazard3_regfile_1w2r.v	Update copyright years	2022-06-09 00:12:01 +01:00
hazard3_width_const.vh	Update copyright years	2022-06-09 00:12:01 +01:00
rv_opcodes.vh	Correct the name and operation of the brev8 (formerly rev.b) instruction	2022-05-20 15:28:18 +01:00