42 lines
1.3 KiB
INI
42 lines
1.3 KiB
INI
# Probe config specific to ULX3S.
|
|
|
|
adapter driver ft232r
|
|
ft232r_vid_pid 0x0403 0x6015
|
|
|
|
# Note adapter_khz doesn't do anything because this is bitbanged JTAG on aux
|
|
# UART pins, but... it's mandatory
|
|
|
|
adapter speed 1000
|
|
|
|
ft232r_tck_num DSR
|
|
ft232r_tms_num DCD
|
|
ft232r_tdi_num RI
|
|
ft232r_tdo_num CTS
|
|
# trst/srst are not used but must have different values than above
|
|
ft232r_trst_num RTS
|
|
ft232r_srst_num DTR
|
|
|
|
# This is the ID for the *FPGA's* chip TAP. (note this ID is for 85F version
|
|
# of ULX3S -- if you have a different ECP5 size you can either enter the
|
|
# correct ID for your ECP5, or remove the -expected-id part). We are going to
|
|
# expose processor debug through a pair of custom DRs on this TAP.
|
|
|
|
set _CHIPNAME lfe5u85
|
|
jtag newtap lfe5u85 hazard3 -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5
|
|
|
|
# We expose the DTMCS/DMI DRs you would find on a normal RISC-V JTAG-DTM via
|
|
# the ECP5 TAP's ER1/ER2 private instructions. As long as you use the correct
|
|
# IR length for the ECP5 TAP, and use the new instructions, the ECP5 TAP
|
|
# looks a lot like a JTAG-DTM.
|
|
|
|
set _TARGETNAME $_CHIPNAME.hazard3
|
|
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
|
|
riscv set_ir dtmcs 0x32
|
|
riscv set_ir dmi 0x38
|
|
|
|
# That's it, it's a normal RISC-V processor now :)
|
|
|
|
gdb_report_data_abort enable
|
|
init
|
|
halt
|