Luke Wren e3b3893cdf Fix partial case overlap lint for shared A/Zbb ALU ops		2024-06-06 06:58:59 +01:00
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hazard3_alu.v	Fix partial case overlap lint for shared A/Zbb ALU ops	2024-06-06 06:58:59 +01:00
hazard3_branchcmp.v	Standardise on ifndef YOSYS around default_nettype wire	2022-08-21 13:22:55 +01:00
hazard3_mul_fast.v	Standardise on ifndef YOSYS around default_nettype wire	2022-08-21 13:22:55 +01:00
hazard3_muldiv_seq.v	Fix width lints in muldiv_seq, onehot_priority_dynamic, and irq_ctrl. All cosmetic.	2024-05-29 15:52:53 +01:00
hazard3_onehot_encode.v	Fix a few width issues identified by verilator lint. All of them gave	2024-05-26 17:32:24 +01:00
hazard3_onehot_priority.v	- Fix signal named priority, which is a keyword in SV	2022-08-07 23:17:03 +01:00
hazard3_onehot_priority_dynamic.v	Fix width lints in muldiv_seq, onehot_priority_dynamic, and irq_ctrl. All cosmetic.	2024-05-29 15:52:53 +01:00
hazard3_priority_encode.v	First pass at implementing the new IRQ controls. Works well enough that the old tests pass :)	2022-08-07 20:51:12 +01:00
hazard3_shift_barrel.v	Standardise on ifndef YOSYS around default_nettype wire	2022-08-21 13:22:55 +01:00
muldiv_model.py	Import from hazard5 9743a1b	2021-05-21 02:34:16 +01:00