405 lines
15 KiB
Verilog
405 lines
15 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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`default_nettype none
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module hazard3_frontend #(
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parameter FIFO_DEPTH = 2, // power of 2, >= 1
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`include "hazard3_config.vh"
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) (
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input wire clk,
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input wire rst_n,
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// Fetch interface
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// addr_vld may be asserted at any time, but after assertion,
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// neither addr nor addr_vld may change until the cycle after addr_rdy.
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// There is no backpressure on the data interface; the front end
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// must ensure it does not request data it cannot receive.
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// addr_rdy and dat_vld may be functions of hready, and
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// may not be used to compute combinational outputs.
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output wire mem_size, // 1'b1 -> 32 bit access
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output wire [W_ADDR-1:0] mem_addr,
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output wire mem_addr_vld,
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input wire mem_addr_rdy,
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input wire [W_DATA-1:0] mem_data,
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input wire mem_data_err,
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input wire mem_data_vld,
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// Jump/flush interface
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// Processor may assert vld at any time. The request will not go through
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// unless rdy is high. Processor *may* alter request during this time.
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// Inputs must not be a function of hready.
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input wire [W_ADDR-1:0] jump_target,
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input wire jump_target_vld,
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output wire jump_target_rdy,
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// Interface to Decode
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// Note reg/wire distinction
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// => decode is providing live feedback on the CIR it is decoding,
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// which we fetched previously
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// This works OK because size is decoded from 2 LSBs of instruction, so cheap.
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output reg [31:0] cir,
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output reg [1:0] cir_vld, // number of valid halfwords in CIR
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input wire [1:0] cir_use, // number of halfwords D intends to consume
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// *may* be a function of hready
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output wire [1:0] cir_err, // Bus error on upper/lower halfword of CIR.
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input wire cir_lock,// Lock-in current contents and level of CIR.
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// Assert simultaneously with a jump request,
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// if decode is going to stall. This stops the CIR
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// from being trashed by incoming fetch data;
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// jump instructions have other side effects besides jumping!
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// Provide the rs1/rs2 register numbers which will be in CIR on the next
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// cycle. These go straight to the register file read ports.
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output wire [4:0] next_regs_rs1,
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output wire [4:0] next_regs_rs2,
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// Debugger instruction injection: instruction fetch is suppressed when in
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// debug halt state, and the DM can then inject instructions into the last
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// entry of the prefetch queue using the vld/rdy handshake.
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input wire debug_mode,
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input wire [W_DATA-1:0] dbg_instr_data,
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input wire dbg_instr_data_vld,
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output wire dbg_instr_data_rdy
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);
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localparam W_BUNDLE = W_DATA / 2;
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parameter W_FIFO_LEVEL = $clog2(FIFO_DEPTH + 1);
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// ----------------------------------------------------------------------------
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// Fetch Queue (FIFO)
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//
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// This is a little different from either a normal sync fifo or sync fwft fifo
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// so it's worth implementing from scratch
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wire jump_now = jump_target_vld && jump_target_rdy;
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// mem has an extra entry which is equal to next-but-last entry, and valid has
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// an extra entry which is constant-0. These are just there to handle loop
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// boundary conditions.
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// err has an error (HRESP) bit associated with each FIFO entry, so that we
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// can correctly speculate and flush fetch errors. The error bit moves
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// through the prefetch queue alongside the corresponding bus data. We sample
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// bus errors like an extra data bit -- fetch continues to speculate forward
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// past an error, and we eventually flush and redirect the frontent if an
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// errored fetch makes it to the execute stage.
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reg [W_DATA-1:0] fifo_mem [0:FIFO_DEPTH];
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reg [FIFO_DEPTH:0] fifo_err;
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reg [FIFO_DEPTH:0] fifo_valid;
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wire [W_DATA-1:0] fifo_wdata = mem_data;
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wire [W_DATA-1:0] fifo_rdata = fifo_mem[0];
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always @ (*) fifo_mem[FIFO_DEPTH] = fifo_wdata;
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wire fifo_full = fifo_valid[FIFO_DEPTH - 1];
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wire fifo_empty = !fifo_valid[0];
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wire fifo_almost_full = FIFO_DEPTH == 1 || (!fifo_valid[FIFO_DEPTH - 1] && fifo_valid[FIFO_DEPTH - 2]);
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wire fifo_push;
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wire fifo_pop;
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wire fifo_dbg_inject = DEBUG_SUPPORT && dbg_instr_data_vld && dbg_instr_data_rdy;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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fifo_valid <= {FIFO_DEPTH+1{1'b0}};
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end else if (jump_now) begin
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fifo_valid <= {FIFO_DEPTH+1{1'b0}};
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end else if (fifo_push || fifo_pop || fifo_dbg_inject) begin
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fifo_valid <= {1'b0, ~(~fifo_valid << (fifo_push || fifo_dbg_inject)) >> fifo_pop};
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end
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end
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always @ (posedge clk) begin: fifo_data_shift
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integer i;
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for (i = 0; i < FIFO_DEPTH; i = i + 1) begin
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if (fifo_pop || (fifo_push && !fifo_valid[i])) begin
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fifo_mem[i] <= fifo_valid[i + 1] ? fifo_mem[i + 1] : fifo_wdata;
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fifo_err[i] <= fifo_err[i + 1] ? fifo_err[i + 1] : mem_data_err;
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end
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end
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// Allow DM to inject instructions directly into the lowest-numbered queue
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// entry. This mux should not extend critical path since it is balanced
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// with the instruction-assembly muxes on the queue bypass path.
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if (fifo_dbg_inject) begin
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fifo_mem[0] <= dbg_instr_data;
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fifo_err[0] <= 1'b0;
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end
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end
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// ----------------------------------------------------------------------------
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// Fetch Request + State Logic
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// Keep track of some useful state of the memory interface
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reg mem_addr_hold;
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reg [1:0] pending_fetches;
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reg [1:0] ctr_flush_pending;
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wire [1:0] pending_fetches_next = pending_fetches + (mem_addr_vld && !mem_addr_hold) - mem_data_vld;
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// Debugger only injects instructions when the frontend is at rest and empty.
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assign dbg_instr_data_rdy = DEBUG_SUPPORT && !fifo_valid[0] && ~|ctr_flush_pending;
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wire cir_must_refill;
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// If fetch data is forwarded past the FIFO, ensure it is not also written to it.
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assign fifo_push = mem_data_vld && ~|ctr_flush_pending && !(cir_must_refill && fifo_empty)
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&& !(DEBUG_SUPPORT && debug_mode);
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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mem_addr_hold <= 1'b0;
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pending_fetches <= 2'h0;
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ctr_flush_pending <= 2'h0;
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end else begin
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`ifdef FORMAL
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assert(ctr_flush_pending <= pending_fetches);
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assert(pending_fetches < 2'd3);
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assert(!(mem_data_vld && !pending_fetches));
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`endif
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mem_addr_hold <= mem_addr_vld && !mem_addr_rdy;
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pending_fetches <= pending_fetches_next;
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if (jump_now) begin
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ctr_flush_pending <= pending_fetches - mem_data_vld;
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end else if (|ctr_flush_pending && mem_data_vld) begin
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ctr_flush_pending <= ctr_flush_pending - 1'b1;
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end
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end
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end
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// Fetch addr runs ahead of the PC, in word increments.
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reg [W_ADDR-1:0] fetch_addr;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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fetch_addr <= RESET_VECTOR;
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end else begin
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if (jump_now) begin
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// Post-increment if jump request is going straight through
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fetch_addr <= {jump_target[W_ADDR-1:2] + (mem_addr_rdy && !mem_addr_hold), 2'b00};
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end else if (mem_addr_vld && mem_addr_rdy) begin
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fetch_addr <= fetch_addr + 32'h4;
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end
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end
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end
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// Using the non-registered version of pending_fetches would improve FIFO
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// utilisation, but create a combinatorial path from hready to address phase!
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wire fetch_stall = fifo_full
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|| fifo_almost_full && |pending_fetches // TODO causes issue with depth 1: only one in flight, so bus rate halved.
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|| pending_fetches > 2'h1;
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// unaligned jump is handled in two different places:
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// - during address phase, offset may be applied to fetch_addr if hready was low when jump_target_vld was high
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// - during data phase, need to assemble CIR differently.
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wire unaligned_jump_now = EXTENSION_C && jump_now && jump_target[1];
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reg unaligned_jump_aph;
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reg unaligned_jump_dph;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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unaligned_jump_aph <= 1'b0;
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unaligned_jump_dph <= 1'b0;
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end else if (EXTENSION_C) begin
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if (mem_addr_rdy || (jump_now && !unaligned_jump_now)) begin
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unaligned_jump_aph <= 1'b0;
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end
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if ((mem_data_vld && ~|ctr_flush_pending && !cir_lock)
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|| (jump_now && !unaligned_jump_now)) begin
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unaligned_jump_dph <= 1'b0;
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end
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if (fifo_pop) begin
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// Following a lock/unlock of the CIR, we may have an unaligned fetch in
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// the FIFO, rather than consuming straight from the bus.
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unaligned_jump_dph <= 1'b0;
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end
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if (unaligned_jump_now) begin
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unaligned_jump_dph <= 1'b1;
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unaligned_jump_aph <= !mem_addr_rdy;
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end
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end
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end
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`ifdef FORMAL
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reg property_after_aligned_jump;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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property_after_aligned_jump <= 1'b0;
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end else begin
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// Every unaligned jump that requires care in aphase also requires care in dphase.
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assert(!(unaligned_jump_aph && !unaligned_jump_dph));
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property_after_aligned_jump <= jump_now && !jump_target[1];
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if (property_after_aligned_jump) begin
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// Make sure these clear properly (have been subtle historic bugs here)
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assert(!unaligned_jump_aph);
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assert(!unaligned_jump_dph);
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end
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end
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end
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`endif
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// Combinatorially generate the address-phase request
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reg reset_holdoff;
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always @ (posedge clk or negedge rst_n)
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if (!rst_n)
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reset_holdoff <= 1'b1;
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else
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reset_holdoff <= 1'b0;
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reg [W_ADDR-1:0] mem_addr_r;
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reg mem_addr_vld_r;
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// Downstream accesses are always word-sized word-aligned.
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assign mem_addr = mem_addr_r;
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assign mem_addr_vld = mem_addr_vld_r && !reset_holdoff;
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assign mem_size = 1'b1;
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always @ (*) begin
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mem_addr_r = {W_ADDR{1'b0}};
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mem_addr_vld_r = 1'b1;
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case (1'b1)
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mem_addr_hold : begin mem_addr_r = fetch_addr; end
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jump_target_vld : begin mem_addr_r = {jump_target[W_ADDR-1:2], 2'b00}; end
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DEBUG_SUPPORT && debug_mode : begin mem_addr_vld_r = 1'b0; end
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!fetch_stall : begin mem_addr_r = fetch_addr; end
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default : begin mem_addr_vld_r = 1'b0; end
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endcase
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end
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assign jump_target_rdy = !mem_addr_hold;
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// ----------------------------------------------------------------------------
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// Instruction assembly yard
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// buf_level is the number of valid halfwords in {hwbuf, cir}.
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reg [1:0] buf_level;
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reg [W_BUNDLE-1:0] hwbuf;
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wire [W_DATA-1:0] fetch_data = fifo_empty ? mem_data : fifo_rdata;
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wire fetch_data_vld = !fifo_empty || (mem_data_vld && ~|ctr_flush_pending && !debug_mode);
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// Shift any recycled instruction data down to backfill D's consumption
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// We don't care about anything which is invalid or will be overlaid with fresh data,
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// so choose these values in a way that minimises muxes
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wire [3*W_BUNDLE-1:0] instr_data_shifted =
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cir_use[1] ? {hwbuf, cir[W_BUNDLE +: W_BUNDLE], hwbuf} :
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cir_use[0] && EXTENSION_C ? {hwbuf, hwbuf, cir[W_BUNDLE +: W_BUNDLE]} :
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{hwbuf, cir};
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// Saturating subtraction: on cir_lock dassertion,
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// buf_level will be 0 but cir_use will be positive!
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wire [1:0] cir_use_clipped = |buf_level ? cir_use : 2'h0;
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wire [1:0] level_next_no_fetch = buf_level - cir_use_clipped;
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// Overlay fresh fetch data onto the shifted/recycled instruction data
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// Again, if something won't be looked at, generate cheapest possible garbage.
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// Don't care if fetch data is valid or not, as will just retry next cycle (as long as flags set correctly)
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wire instr_fetch_overlay_blocked = cir_lock || (level_next_no_fetch[1] && !unaligned_jump_dph);
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wire [3*W_BUNDLE-1:0] instr_data_plus_fetch =
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instr_fetch_overlay_blocked ? instr_data_shifted :
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unaligned_jump_dph && EXTENSION_C ? {instr_data_shifted[W_BUNDLE +: 2*W_BUNDLE], fetch_data[W_BUNDLE +: W_BUNDLE]} :
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level_next_no_fetch[0] && EXTENSION_C ? {fetch_data, instr_data_shifted[0 +: W_BUNDLE]} :
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{instr_data_shifted[2*W_BUNDLE +: W_BUNDLE], fetch_data};
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assign cir_must_refill = !cir_lock && !level_next_no_fetch[1];
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assign fifo_pop = cir_must_refill && !fifo_empty;
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wire [1:0] buf_level_next =
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jump_now || |ctr_flush_pending || cir_lock ? 2'h0 :
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fetch_data_vld && unaligned_jump_dph ? 2'h1 :
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buf_level + {cir_must_refill && fetch_data_vld, 1'b0} - cir_use_clipped;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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buf_level <= 2'h0;
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cir_vld <= 2'h0;
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end else begin
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`ifdef FORMAL
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assert(cir_vld <= 2);
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assert(cir_use <= cir_vld);
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`endif
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// Update CIR flags
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buf_level <= buf_level_next;
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if (!cir_lock)
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cir_vld <= buf_level_next & ~(buf_level_next >> 1'b1);
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// Update CIR contents
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end
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end
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// No need to reset these as they will be written before first use
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always @ (posedge clk)
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{hwbuf, cir} <= instr_data_plus_fetch;
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`ifdef FORMAL
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reg [1:0] property_past_buf_level; // Workaround for weird non-constant $past reset issue
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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property_past_buf_level <= 2'h0;
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end else begin
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property_past_buf_level <= buf_level;
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// We fetch 32 bits per cycle, max. If this happens it's due to negative overflow.
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if (property_past_buf_level == 2'h0)
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assert(buf_level != 2'h3);
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end
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end
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`endif
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// Also keep track of bus errors associated with CIR contents, shifted in the
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// same way as instruction data. Errors may come straight from the bus, or
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// may be buffered in the prefetch queue.
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wire fetch_bus_err = fifo_empty ? mem_data_err : fifo_err[0];
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reg [2:0] cir_bus_err;
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wire [2:0] cir_bus_err_shifted =
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cir_use[1] ? cir_bus_err >> 2 :
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cir_use[0] && EXTENSION_C ? cir_bus_err >> 1 : cir_bus_err;
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wire [2:0] cir_bus_err_plus_fetch =
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instr_fetch_overlay_blocked ? cir_bus_err_shifted :
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unaligned_jump_dph && EXTENSION_C ? {cir_bus_err_shifted[2:1], fetch_bus_err} :
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level_next_no_fetch && EXTENSION_C ? {{2{fetch_bus_err}}, cir_bus_err_shifted[0]} :
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{cir_bus_err_shifted[2], {2{fetch_bus_err}}};
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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cir_bus_err <= 3'h0;
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end else if (CSR_M_TRAP) begin
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cir_bus_err <= cir_bus_err_plus_fetch;
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end
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end
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assign cir_err = cir_bus_err[1:0];
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// ----------------------------------------------------------------------------
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// Register number predecode
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wire [31:0] next_instr = instr_data_plus_fetch[31:0];
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wire next_instr_is_32bit = next_instr[1:0] == 2'b11;
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assign next_regs_rs1 =
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next_instr_is_32bit ? next_instr[19:15] : // 32-bit R, S, B formats
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next_instr[1:0] == 2'b00 && next_instr[14:13] == 2'b00 ? 5'd2 : // c.addi4spn + don't care
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next_instr[1:0] == 2'b01 && next_instr[15 ] == 1'b0 ? next_instr[11:7] : // c.addi, c.addi16sp + don't care (jal, li)
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next_instr[1:0] == 2'b10 && next_instr[14 ] == 1'b1 ? 5'd2 : // c.lwsp, c.lwsp + don't care
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next_instr[1:0] == 2'b10 ? next_instr[11:7] :
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{2'b01, next_instr[9:7]};
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assign next_regs_rs2 =
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next_instr_is_32bit ? next_instr[24:20] :
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next_instr[1:0] == 2'b10 ? next_instr[6:2] : {2'b01, next_instr[4:2]};
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endmodule
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`default_nettype wire
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