Luke Wren 12851d3742 Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set		2021-05-30 19:52:46 +01:00
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formal	Add instruction fetch match check	2021-05-30 11:22:36 +01:00
sim	Bring mtvec vectoring modes in line with spec: all exceptions go to mtvec, IRQs are optionally vectored away from it if mtvec LSB is set	2021-05-30 19:52:46 +01:00
.gitignore	Import from hazard5 9743a1b	2021-05-21 02:34:16 +01:00