48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
#include "tb_cxxrtl_io.h"
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#include "hazard3_csr.h"
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// Check misaligned halfword stores generate exception with correct mcause
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/*EXPECTED-OUTPUT***************************************************************
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Store halfword, 1 byte offset
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-> exception, mcause = 6
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Target value: ffffffff
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Store halfword, 3 byte offset
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-> exception, mcause = 6
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Target value: ffffffff
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Aligned store halfword, sanity check
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Target value: ffff0000
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Target value: 00000000
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*******************************************************************************/
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int main() {
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volatile uint32_t target_word = -1u;
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tb_puts("Store halfword, 1 byte offset\n");
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asm volatile ("sh zero, 1(%0)" : : "r" (&target_word));
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tb_printf("Target value: %08x\n", target_word);
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tb_puts("Store halfword, 3 byte offset\n");
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asm volatile ("sh zero, 3(%0)" : : "r" (&target_word));
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tb_printf("Target value: %08x\n", target_word);
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tb_puts("Aligned store halfword, sanity check\n");
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asm volatile ("sh zero, 0(%0)" : : "r" (&target_word));
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tb_printf("Target value: %08x\n", target_word);
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asm volatile ("sh zero, 2(%0)" : : "r" (&target_word));
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tb_printf("Target value: %08x\n", target_word);
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return 0;
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}
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void __attribute__((interrupt)) handle_exception() {
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tb_printf("-> exception, mcause = %u\n", read_csr(mcause));
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write_csr(mcause, 0);
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if ((*(uint16_t*)read_csr(mepc) & 0x3) == 0x3) {
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write_csr(mepc, read_csr(mepc) + 4);
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}
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else {
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write_csr(mepc, read_csr(mepc) + 2);
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}
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}
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