242 lines
8.1 KiB
Verilog
242 lines
8.1 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021-2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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`default_nettype none
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module hazard3_alu #(
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`include "hazard3_config.vh"
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,
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`include "hazard3_width_const.vh"
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) (
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input wire [W_ALUOP-1:0] aluop,
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input wire [W_DATA-1:0] op_a,
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input wire [W_DATA-1:0] op_b,
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output reg [W_DATA-1:0] result,
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output wire cmp
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);
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`include "hazard3_ops.vh"
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// ----------------------------------------------------------------------------
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// Fiddle around with add/sub, comparisons etc (all related).
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function msb;
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input [W_DATA-1:0] x;
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begin
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msb = x[W_DATA-1];
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end
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endfunction
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wire sub = !(aluop == ALUOP_ADD || (|EXTENSION_ZBA && (
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aluop == ALUOP_SH1ADD || aluop == ALUOP_SH2ADD || aluop == ALUOP_SH3ADD
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)));
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wire inv_op_b = sub && !(
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aluop == ALUOP_AND || aluop == ALUOP_OR || aluop == ALUOP_XOR || aluop == ALUOP_RS2
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);
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wire [W_DATA-1:0] op_a_shifted =
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|EXTENSION_ZBA && aluop == ALUOP_SH1ADD ? op_a << 1 :
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|EXTENSION_ZBA && aluop == ALUOP_SH2ADD ? op_a << 2 :
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|EXTENSION_ZBA && aluop == ALUOP_SH3ADD ? op_a << 3 : op_a;
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wire [W_DATA-1:0] op_b_inv = op_b ^ {W_DATA{inv_op_b}};
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wire [W_DATA-1:0] sum = op_a_shifted + op_b_inv + sub;
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wire [W_DATA-1:0] op_xor = op_a ^ op_b;
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wire cmp_is_unsigned = aluop == ALUOP_LTU ||
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|EXTENSION_ZBB && aluop == ALUOP_MAXU ||
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|EXTENSION_ZBB && aluop == ALUOP_MINU;
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wire lt = msb(op_a) == msb(op_b) ? msb(sum) :
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cmp_is_unsigned ? msb(op_b) :
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msb(op_a) ;
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assign cmp = aluop == ALUOP_SUB ? |op_xor : lt;
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// ----------------------------------------------------------------------------
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// Separate units for shift, ctz etc
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wire [W_DATA-1:0] shift_dout;
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wire shift_right_nleft = aluop == ALUOP_SRL || aluop == ALUOP_SRA ||
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|EXTENSION_ZBB && aluop == ALUOP_ROR ||
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|EXTENSION_ZBS && aluop == ALUOP_BEXT;
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wire shift_arith = aluop == ALUOP_SRA;
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wire shift_rotate = |EXTENSION_ZBB & (aluop == ALUOP_ROR || aluop == ALUOP_ROL);
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hazard3_shift_barrel #(
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`include "hazard3_config_inst.vh"
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) shifter (
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.din (op_a),
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.shamt (op_b[4:0]),
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.right_nleft (shift_right_nleft),
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.rotate (shift_rotate),
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.arith (shift_arith),
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.dout (shift_dout)
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);
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reg [W_DATA-1:0] op_a_rev;
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always @ (*) begin: rev_op_a
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integer i;
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for (i = 0; i < W_DATA; i = i + 1) begin
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op_a_rev[i] = op_a[W_DATA - 1 - i];
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end
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end
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// "leading" means starting at MSB. This is an LSB-first priority encoder, so
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// "leading" is reversed and "trailing" is not.
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wire [W_DATA-1:0] ctz_search_mask = aluop == ALUOP_CLZ ? op_a_rev : op_a;
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wire [W_SHAMT:0] ctz_clz;
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hazard3_priority_encode #(
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.W_REQ (W_DATA)
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) ctz_priority_encode (
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.req (ctz_search_mask),
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.gnt (ctz_clz[W_SHAMT-1:0])
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);
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// Special case: all-zeroes returns XLEN
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assign ctz_clz[W_SHAMT] = ~|op_a;
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reg [W_SHAMT:0] cpop;
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always @ (*) begin: cpop_count
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integer i;
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cpop = {W_SHAMT+1{1'b0}};
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for (i = 0; i < W_DATA; i = i + 1) begin
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cpop = cpop + {{W_SHAMT{1'b0}}, op_a[i]};
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end
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end
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reg [2*W_DATA-1:0] clmul;
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always @ (*) begin: clmul_mul
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integer i;
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clmul = {2*W_DATA{1'b0}};
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for (i = 0; i < W_DATA; i = i + 1) begin
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clmul = clmul ^ (({{W_DATA{1'b0}}, op_a} << i) & {2*W_DATA{op_b[i]}});
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end
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end
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reg [W_DATA-1:0] zip;
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reg [W_DATA-1:0] unzip;
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always @ (*) begin: do_zip_unzip
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integer i;
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for (i = 0; i < W_DATA; i = i + 1) begin
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zip[i] = op_a[{i[0], i[4:1]}]; // Alternate high/low halves
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unzip[i] = op_a[{i[3:0], i[4]}]; // All even then all odd
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end
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end
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// ----------------------------------------------------------------------------
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// Output mux, with simple operations inline
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// iCE40: We can implement all bitwise ops with 1 LUT4/bit total, since each
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// result bit uses only two operand bits. Much better than feeding each into
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// main mux tree. Doesn't matter for big-LUT FPGAs or for implementations with
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// bitmanip extensions enabled.
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reg [W_DATA-1:0] bitwise;
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always @ (*) begin: bitwise_ops
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case (aluop[1:0])
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ALUOP_AND[1:0]: bitwise = op_a & op_b_inv;
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ALUOP_OR [1:0]: bitwise = op_a | op_b_inv;
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ALUOP_XOR[1:0]: bitwise = op_a ^ op_b_inv;
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ALUOP_RS2[1:0]: bitwise = op_b_inv;
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endcase
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end
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wire [W_DATA-1:0] zbs_mask = {{W_DATA-1{1'b0}}, 1'b1} << op_b[W_SHAMT-1:0];
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always @ (*) begin
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casez ({|EXTENSION_A, |EXTENSION_ZBA, |EXTENSION_ZBB, |EXTENSION_ZBC, |EXTENSION_ZBS, |EXTENSION_ZBKB, aluop})
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// Base ISA
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{6'bzzzzzz, ALUOP_ADD }: result = sum;
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{6'bzzzzzz, ALUOP_SUB }: result = sum;
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{6'bzzzzzz, ALUOP_LT }: result = {{W_DATA-1{1'b0}}, lt};
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{6'bzzzzzz, ALUOP_LTU }: result = {{W_DATA-1{1'b0}}, lt};
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{6'bzzzzzz, ALUOP_SRL }: result = shift_dout;
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{6'bzzzzzz, ALUOP_SRA }: result = shift_dout;
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{6'bzzzzzz, ALUOP_SLL }: result = shift_dout;
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// A (duplicates of Zbb)
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{6'b1zzzzz, ALUOP_MAX }: result = lt ? op_b : op_a;
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{6'b1zzzzz, ALUOP_MAXU }: result = lt ? op_b : op_a;
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{6'b1zzzzz, ALUOP_MIN }: result = lt ? op_a : op_b;
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{6'b1zzzzz, ALUOP_MINU }: result = lt ? op_a : op_b;
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// Zba
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{6'bz1zzzz, ALUOP_SH1ADD }: result = sum;
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{6'bz1zzzz, ALUOP_SH2ADD }: result = sum;
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{6'bz1zzzz, ALUOP_SH3ADD }: result = sum;
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// Zbb
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{6'bzz1zzz, ALUOP_ANDN }: result = bitwise;
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{6'bzz1zzz, ALUOP_ORN }: result = bitwise;
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{6'bzz1zzz, ALUOP_XNOR }: result = bitwise;
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{6'bzz1zzz, ALUOP_CLZ }: result = {{W_DATA-W_SHAMT-1{1'b0}}, ctz_clz};
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{6'bzz1zzz, ALUOP_CTZ }: result = {{W_DATA-W_SHAMT-1{1'b0}}, ctz_clz};
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{6'bzz1zzz, ALUOP_CPOP }: result = {{W_DATA-W_SHAMT-1{1'b0}}, cpop};
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{6'bzz1zzz, ALUOP_MAX }: result = lt ? op_b : op_a;
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{6'bzz1zzz, ALUOP_MAXU }: result = lt ? op_b : op_a;
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{6'bzz1zzz, ALUOP_MIN }: result = lt ? op_a : op_b;
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{6'bzz1zzz, ALUOP_MINU }: result = lt ? op_a : op_b;
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{6'bzz1zzz, ALUOP_SEXT_B }: result = {{W_DATA-8{op_a[7]}}, op_a[7:0]};
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{6'bzz1zzz, ALUOP_SEXT_H }: result = {{W_DATA-16{op_a[15]}}, op_a[15:0]};
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{6'bzz1zzz, ALUOP_ZEXT_H }: result = {{W_DATA-16{1'b0}}, op_a[15:0]};
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{6'bzz1zzz, ALUOP_ORC_B }: result = {{8{|op_a[31:24]}}, {8{|op_a[23:16]}}, {8{|op_a[15:8]}}, {8{|op_a[7:0]}}};
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{6'bzz1zzz, ALUOP_REV8 }: result = {op_a[7:0], op_a[15:8], op_a[23:16], op_a[31:24]};
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{6'bzz1zzz, ALUOP_ROL }: result = shift_dout;
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{6'bzz1zzz, ALUOP_ROR }: result = shift_dout;
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// Zbc
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{6'bzzz1zz, ALUOP_CLMUL }: result = clmul[W_DATA-1:0];
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{6'bzzz1zz, ALUOP_CLMULH }: result = clmul[2*W_DATA-1:W_DATA];
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{6'bzzz1zz, ALUOP_CLMULR }: result = clmul[2*W_DATA-2:W_DATA-1];
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// Zbs
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{6'bzzzz1z, ALUOP_BCLR }: result = op_a & ~zbs_mask;
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{6'bzzzz1z, ALUOP_BSET }: result = op_a | zbs_mask;
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{6'bzzzz1z, ALUOP_BINV }: result = op_a ^ zbs_mask;
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{6'bzzzz1z, ALUOP_BEXT }: result = {{W_DATA-1{1'b0}}, shift_dout[0]};
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// Zbkb
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{6'bzzzzz1, ALUOP_PACK }: result = {op_b[15:0], op_a[15:0]};
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{6'bzzzzz1, ALUOP_PACKH }: result = {{W_DATA-16{1'b0}}, op_b[7:0], op_a[7:0]};
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{6'bzzzzz1, ALUOP_BREV8 }: result = {op_a_rev[7:0], op_a_rev[15:8], op_a_rev[23:16], op_a_rev[31:24]};
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{6'bzzzzz1, ALUOP_UNZIP }: result = unzip;
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{6'bzzzzz1, ALUOP_ZIP }: result = zip;
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default: result = bitwise;
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endcase
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end
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// ----------------------------------------------------------------------------
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// Properties for base-ISA instructions
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`ifdef HAZARD3_ASSERTIONS
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`ifndef RISCV_FORMAL
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// Really we're just interested in the shifts and comparisons, as these are
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// the nontrivial ones. However, easier to test everything!
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wire clk;
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always @ (posedge clk) begin
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case(aluop)
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default: begin end
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ALUOP_ADD: assert(result == op_a + op_b);
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ALUOP_SUB: assert(result == op_a - op_b);
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ALUOP_LT: assert(result == $signed(op_a) < $signed(op_b));
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ALUOP_LTU: assert(result == op_a < op_b);
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ALUOP_AND: assert(result == (op_a & op_b));
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ALUOP_OR: assert(result == (op_a | op_b));
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ALUOP_XOR: assert(result == (op_a ^ op_b));
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ALUOP_SRL: assert(result == op_a >> op_b[4:0]);
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ALUOP_SRA: assert($signed(result) == $signed(op_a) >>> $signed(op_b[4:0]));
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ALUOP_SLL: assert(result == op_a << op_b[4:0]);
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endcase
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end
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`endif
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`endif
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endmodule
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`default_nettype wire
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