Luke Wren 64d9f4a111 Add tests for execution of mret and wfi in U mode		2022-05-24 22:14:20 +01:00
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hazard3_csr.h	Add tests for execution of mret and wfi in U mode	2022-05-24 22:14:20 +01:00
init.S	Add exclusives monitor to testbench	2021-12-17 17:03:35 +00:00
memmap.ld	Add RISC-V debug tests	2021-07-22 17:50:04 +01:00
src_only_app.mk	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
tb_cxxrtl_io.h	Add exclusives monitor to testbench	2021-12-17 17:03:35 +00:00