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Luke Wren 9787c604ad Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)		2022-07-30 17:31:53 +01:00
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embench-iot@d85ddd2e94	Bump embench for script fixes/improvements	2022-07-07 18:29:37 +01:00
Readme.md	Add missing ebreaku field to dcsr (U-mode counterpart to ebreakm)	2022-07-30 17:31:53 +01:00

Readme.md

Embench

To run these benchmarks, first make sure the embench-iot submodule is checked out, then:

cd embench-iot
# Make sure testbench is up to date
make -C ../../tb_cxxrtl tb
./build_all.py --arch riscv32 --chip hazard3 --board hazard3tb
./benchmark_speed.py --target-module run_hazard3tb --timeout 120

The compiler specified in config/riscv32/chips/hazard3/chip.cfg is /opt/riscv/unstable/bin/riscv32-unknown-elf-gcc, which is where I have an unstable GCC 12 build installed on my machine. You need to have a recent upstream master build to support the Zba/Zbb/Zbc/Zbs instructions. If you don't care about these, you can use whatever riscv32-unknown-elf compiler you have, and also edit cflags in that .cfg file to not include the bitmanip extensions in march.

You can also add --sim-parallel to the benchmark_speed for faster simulations.