Luke Wren e68d8a6cd6 Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.		2022-06-13 01:23:32 +01:00
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fpga	Beef up the ULX3S SoC again now that atomics aren't so disastrous for timing	2021-12-18 02:41:50 +00:00
libfpga@9d50e12e01	Bump libfpga for correct bus error response from AHBL splitter in example SoC	2021-11-28 01:35:52 +00:00
soc	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00
synth	Remove flash XIP from example_soc -- keep it simple and reclaim UART FTDI pins on iCEBreaker	2021-11-21 15:55:52 +00:00
icebreaker-openocd.cfg	Small code cleanup	2021-07-24 10:08:27 +01:00
ulx3s-openocd.cfg	Working ECP5 debug, seems a bit slow but maybe just due to bitbanged FT231X JTAG.	2021-07-23 18:32:47 +01:00