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arith
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Correct the name and operation of the brev8 (formerly rev.b) instruction
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2022-05-20 15:28:18 +01:00 |
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debug
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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peri
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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hazard3.f
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Perf option for dedicated branch comparator
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2022-04-02 11:40:47 +01:00 |
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hazard3_config.vh
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Sketch in PMP implementation
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2022-05-23 18:06:23 +01:00 |
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hazard3_config_inst.vh
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Sketch in PMP implementation
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2022-05-23 18:06:23 +01:00 |
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hazard3_core.v
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Fix IALIGN fault to trap on the control flow instruction instead of its target
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2022-05-23 16:25:43 +01:00 |
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hazard3_cpu_1port.v
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Add single-port bus compliance. Fix adapter not re-arbitrating following an ERROR response, causing a squashed younger load-store to remain presented to the bus.
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2021-12-18 15:41:05 +00:00 |
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hazard3_cpu_2port.v
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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hazard3_csr.v
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Split CSR addresses into separate header file
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2022-05-23 15:54:37 +01:00 |
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hazard3_csr_addr.vh
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Sketch in PMP implementation
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2022-05-23 18:06:23 +01:00 |
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hazard3_decode.v
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Correct the name and operation of the brev8 (formerly rev.b) instruction
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2022-05-20 15:28:18 +01:00 |
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hazard3_frontend.v
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Stronger property for correct predecode
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2022-04-05 08:18:00 +01:00 |
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hazard3_instr_decompress.v
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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hazard3_ops.vh
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Correct the name and operation of the brev8 (formerly rev.b) instruction
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2022-05-20 15:28:18 +01:00 |
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hazard3_pmp.v
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Sketch in PMP implementation
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2022-05-23 18:06:23 +01:00 |
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hazard3_regfile_1w2r.v
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Remove unused FAKE_DUALPORT option from regfile
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2022-05-23 16:22:01 +01:00 |
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hazard3_width_const.vh
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New license headers: DWTFPL -> Apache 2.0
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2021-12-13 23:23:40 +00:00 |
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rv_opcodes.vh
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Correct the name and operation of the brev8 (formerly rev.b) instruction
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2022-05-20 15:28:18 +01:00 |
5466c8131e