79 lines
3.1 KiB
Systemverilog
79 lines
3.1 KiB
Systemverilog
// Hazard3 CPU configuration parameters
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// To configure Hazard3 you can either edit this file, or set parameters on
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// your top-level instantiation, it's up to you. These parameters are all
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// plumbed through Hazard3's internal hierarchy to the appropriate places.
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// ----------------------------------------------------------------------------
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// Reset state configuration
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// RESET_VECTOR: Address of first instruction executed.
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parameter RESET_VECTOR = 32'h0,
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// MTVEC_INIT: Initial value of trap vector base. Bits clear in MTVEC_WMASK
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// will never change from this initial value. Bits set in MTVEC_WMASK can be
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// written/set/cleared as normal. Note that, if CSR_M_TRAP is set, MTVEC_INIT
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// should probably have a different value from RESET_VECTOR.
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parameter MTVEC_INIT = 32'h00000000,
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// ----------------------------------------------------------------------------
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// RISC-V ISA and CSR support
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// EXTENSION_C: Support for compressed (variable-width) instructions
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parameter EXTENSION_C = 1,
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// EXTENSION_M: Support for hardware multiply/divide/modulo instructions
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parameter EXTENSION_M = 1,
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// CSR_M_MANDATORY: Bare minimum CSR support e.g. misa. Spec says must = 1 if
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// CSRs are present, but I won't tell anyone.
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parameter CSR_M_MANDATORY = 1,
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// CSR_M_TRAP: Include M-mode trap-handling CSRs, and enable trap support.
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parameter CSR_M_TRAP = 1,
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// CSR_COUNTER: Include performance counters and relevant M-mode CSRs
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parameter CSR_COUNTER = 0,
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// ----------------------------------------------------------------------------
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// ID registers
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// JEDEC JEP106-compliant vendor ID, can be left at 0 if "not implemented or
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// that this is a non-commercial implementation" (RISC-V spec).
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// 31:7 is continuation code count, 6:0 is ID. Parity bit is not stored.
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parameter MVENDORID_VAL = 32'h0,
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// Architecture ID for Hazard3, currently 0 because unregistered. (TODO)
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parameter MARCHID_VAL = 32'h0,
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// Implementation ID for this specific version of Hazard3. Git hash is perfect.
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parameter MIMPID_VAL = 32'h0,
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// ----------------------------------------------------------------------------
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// Performance/size options
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// REDUCED_BYPASS: Remove all forwarding paths except X->X (so back-to-back
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// ALU ops can still run at 1 CPI), to save area.
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parameter REDUCED_BYPASS = 0,
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// MULDIV_UNROLL: Bits per clock for multiply/divide circuit, if present. Must
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// be a power of 2.
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parameter MULDIV_UNROLL = 1,
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// MUL_FAST: Use single-cycle multiply circuit for MUL instructions, retiring
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// to stage M. The sequential multiply/divide circuit is still used for
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// MULH/MULHU/MULHSU.
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parameter MUL_FAST = 0,
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// MTVEC_WMASK: Mask of which bits in MTVEC are modifiable. Save gates by
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// making trap vector base partly fixed (legal, as it's WARL). Note the entire
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// vector table must always be aligned to its size, rounded up to a power of
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// two, so careful with the low-order bits.
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parameter MTVEC_WMASK = 32'hfffff000,
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// ----------------------------------------------------------------------------
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// Port size parameters (do not modify)
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parameter W_ADDR = 32, // Do not modify
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parameter W_DATA = 32 // Do not modify
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