183 lines
5.6 KiB
Verilog
183 lines
5.6 KiB
Verilog
/**********************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*********************************************************************/
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// Dual-ported top level file for Hazard3 CPU. This file instantiates the
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// Hazard3 core, and interfaces its instruction fetch and load/store signals
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// to a pair of AHB-Lite master ports.
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module hazard3_cpu_2port #(
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`include "hazard3_config.vh"
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) (
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// Global signals
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input wire clk,
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input wire rst_n,
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`ifdef RISCV_FORMAL
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`RVFI_OUTPUTS ,
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`endif
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// Instruction fetch port
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output wire [W_ADDR-1:0] i_haddr,
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output wire i_hwrite,
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output wire [1:0] i_htrans,
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output wire [2:0] i_hsize,
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output wire [2:0] i_hburst,
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output wire [3:0] i_hprot,
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output wire i_hmastlock,
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input wire i_hready,
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input wire i_hresp,
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output wire [W_DATA-1:0] i_hwdata,
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input wire [W_DATA-1:0] i_hrdata,
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// Load/store port
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output wire [W_ADDR-1:0] d_haddr,
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output wire d_hwrite,
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output wire [1:0] d_htrans,
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output wire [2:0] d_hsize,
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output wire [2:0] d_hburst,
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output wire [3:0] d_hprot,
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output wire d_hmastlock,
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input wire d_hready,
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input wire d_hresp,
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output wire [W_DATA-1:0] d_hwdata,
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input wire [W_DATA-1:0] d_hrdata,
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// Level-sensitive interrupt sources
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input wire [NUM_IRQ-1:0] irq, // -> mip.meip
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input wire soft_irq, // -> mip.msip
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input wire timer_irq // -> mip.mtip
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);
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// ----------------------------------------------------------------------------
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// Processor core
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// Instruction fetch signals
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wire core_aph_req_i;
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wire core_aph_panic_i; // unused as there's no arbitration
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wire core_aph_ready_i;
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wire core_dph_ready_i;
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wire core_dph_err_i;
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wire [2:0] core_hsize_i;
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wire [W_ADDR-1:0] core_haddr_i;
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wire [W_DATA-1:0] core_rdata_i;
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// Load/store signals
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wire core_aph_req_d;
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wire core_aph_ready_d;
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wire core_dph_ready_d;
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wire core_dph_err_d;
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wire [W_ADDR-1:0] core_haddr_d;
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wire [2:0] core_hsize_d;
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wire core_hwrite_d;
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wire [W_DATA-1:0] core_wdata_d;
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wire [W_DATA-1:0] core_rdata_d;
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hazard3_core #(
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`include "hazard3_config_inst.vh"
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) core (
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.clk (clk),
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.rst_n (rst_n),
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`ifdef RISCV_FORMAL
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`RVFI_CONN ,
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`endif
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.bus_aph_req_i (core_aph_req_i),
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.bus_aph_panic_i (core_aph_panic_i),
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.bus_aph_ready_i (core_aph_ready_i),
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.bus_dph_ready_i (core_dph_ready_i),
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.bus_dph_err_i (core_dph_err_i),
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.bus_hsize_i (core_hsize_i),
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.bus_haddr_i (core_haddr_i),
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.bus_rdata_i (core_rdata_i),
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.bus_aph_req_d (core_aph_req_d),
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.bus_aph_ready_d (core_aph_ready_d),
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.bus_dph_ready_d (core_dph_ready_d),
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.bus_dph_err_d (core_dph_err_d),
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.bus_haddr_d (core_haddr_d),
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.bus_hsize_d (core_hsize_d),
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.bus_hwrite_d (core_hwrite_d),
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.bus_wdata_d (core_wdata_d),
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.bus_rdata_d (core_rdata_d),
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.irq (irq),
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.soft_irq (soft_irq),
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.timer_irq (timer_irq)
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);
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// ----------------------------------------------------------------------------
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// Instruction port
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localparam HTRANS_IDLE = 2'b00;
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localparam HTRANS_NSEQ = 2'b10;
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assign i_haddr = core_haddr_i;
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assign i_htrans = core_aph_req_i ? HTRANS_NSEQ : HTRANS_IDLE;
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assign i_hsize = core_hsize_i;
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reg dphase_active_i;
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always @ (posedge clk or negedge rst_n)
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if (!rst_n)
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dphase_active_i <= 1'b0;
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else if (i_hready)
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dphase_active_i <= core_aph_req_i;
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assign core_aph_ready_i = i_hready && core_aph_req_i;
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assign core_dph_ready_i = i_hready && dphase_active_i;
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assign core_dph_err_i = i_hready && dphase_active_i && i_hresp;
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assign core_rdata_i = i_hrdata;
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assign i_hwrite = 1'b0;
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assign i_hburst = 3'h0;
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assign i_hprot = 4'b0010;
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assign i_hmastlock = 1'b0;
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assign i_hwdata = {W_DATA{1'b0}};
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// ----------------------------------------------------------------------------
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// Load/store port
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assign d_haddr = core_haddr_d;
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assign d_htrans = core_aph_req_d ? HTRANS_NSEQ : HTRANS_IDLE;
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assign d_hwrite = core_hwrite_d;
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assign d_hsize = core_hsize_d;
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reg dphase_active_d;
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always @ (posedge clk or negedge rst_n)
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if (!rst_n)
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dphase_active_d <= 1'b0;
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else if (d_hready)
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dphase_active_d <= core_aph_req_d;
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assign core_aph_ready_d = d_hready && core_aph_req_d;
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assign core_dph_ready_d = d_hready && dphase_active_d;
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assign core_dph_err_d = d_hready && dphase_active_d && d_hresp;
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assign core_rdata_d = d_hrdata;
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assign d_hwdata = core_wdata_d;
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assign d_hburst = 3'h0;
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assign d_hprot = 4'b0010;
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assign d_hmastlock = 1'b0;
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endmodule
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