94 lines
2.4 KiB
Verilog
94 lines
2.4 KiB
Verilog
/**********************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2021 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*********************************************************************/
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// FPGA toplevel for ../soc/example_soc.v on an iCEBreaker dev board
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`default_nettype none
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module fpga_icebreaker (
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input wire clk_osc,
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// No external trst_n as iCEBreaker can't easily drive it from FTDI, so we
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// generate a pulse internally from FPGA PoR.
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input wire tck,
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input wire tms,
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input wire tdi,
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output wire tdo,
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output wire led,
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output wire mirror_tck,
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output wire mirror_tms,
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output wire mirror_tdi,
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output wire mirror_tdo,
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output wire uart_tx,
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input wire uart_rx
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);
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assign mirror_tck = tck;
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assign mirror_tms = tms;
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assign mirror_tdi = tdi;
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assign mirror_tdo = tdo;
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wire clk_sys = clk_osc;
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wire rst_n_sys;
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wire trst_n;
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fpga_reset #(
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.SHIFT (3)
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) rstgen (
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.clk (clk_sys),
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.force_rst_n (1'b1),
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.rst_n (rst_n_sys)
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);
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reset_sync trst_sync_u (
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.clk (tck),
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.rst_n_in (rst_n_sys),
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.rst_n_out (trst_n)
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);
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activity_led #(
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.WIDTH (1 << 16),
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.ACTIVE_LEVEL (1'b0)
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) tck_led_u (
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.clk (clk_sys),
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.rst_n (rst_n_sys),
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.i (tck),
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.o (led)
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);
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example_soc #(
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.MUL_FAST (1),
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.EXTENSION_C (0)
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) soc_u (
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.clk (clk_sys),
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.rst_n (rst_n_sys),
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.tck (tck),
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.trst_n (trst_n),
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.tms (tms),
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.tdi (tdi),
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.tdo (tdo),
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.uart_tx (uart_tx),
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.uart_rx (uart_rx)
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);
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endmodule
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