214 lines
7.1 KiB
Verilog
214 lines
7.1 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021-2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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`default_nettype none
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module hazard3_instr_decompress #(
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`include "hazard3_config.vh"
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) (
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input wire [31:0] instr_in,
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output reg instr_is_32bit,
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output reg [31:0] instr_out,
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output reg invalid
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);
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`include "rv_opcodes.vh"
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localparam W_REGADDR = 5;
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localparam PASSTHROUGH = ~|EXTENSION_C;
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// Long-register formats: cr, ci, css
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// Short-register formats: ciw, cl, cs, cb, cj
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wire [W_REGADDR-1:0] rd_l = instr_in[11:7];
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wire [W_REGADDR-1:0] rs1_l = instr_in[11:7];
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wire [W_REGADDR-1:0] rs2_l = instr_in[6:2];
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wire [W_REGADDR-1:0] rd_s = {2'b01, instr_in[4:2]};
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wire [W_REGADDR-1:0] rs1_s = {2'b01, instr_in[9:7]};
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wire [W_REGADDR-1:0] rs2_s = {2'b01, instr_in[4:2]};
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// Mapping of cx -> x immediate formats (we are *expanding* instructions, not
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// decoding them):
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wire [31:0] imm_ci = {
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{7{instr_in[12]}},
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instr_in[6:2],
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20'h00000
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};
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wire [31:0] imm_cj = {
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instr_in[12],
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instr_in[8],
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instr_in[10:9],
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instr_in[6],
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instr_in[7],
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instr_in[2],
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instr_in[11],
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instr_in[5:3],
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{9{instr_in[12]}},
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12'h000
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};
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wire [31:0] imm_cb ={
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{4{instr_in[12]}},
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instr_in[6:5],
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instr_in[2],
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13'h0000,
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instr_in[11:10],
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instr_in[4:3],
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instr_in[12],
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7'h00
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};
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wire [31:0] imm_c_lb = {
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10'h0,
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instr_in[5],
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instr_in[6],
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20'h00000
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};
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wire [31:0] imm_c_lh = {
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10'h000,
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instr_in[5],
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1'b0,
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20'h00000
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};
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function [31:0] rfmt_rd; input [4:0] rd; begin rfmt_rd = {20'h00000, rd, 7'h00}; end endfunction
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function [31:0] rfmt_rs1; input [4:0] rs1; begin rfmt_rs1 = {12'h000, rs1, 15'h0000}; end endfunction
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function [31:0] rfmt_rs2; input [4:0] rs2; begin rfmt_rs2 = {7'h00, rs2, 20'h00000}; end endfunction
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generate
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if (PASSTHROUGH) begin: instr_passthrough
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always @ (*) begin
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instr_is_32bit = 1'b1;
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instr_out = instr_in;
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invalid = 1'b0;
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end
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end else begin: instr_decompress
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always @ (*) begin
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if (instr_in[1:0] == 2'b11) begin
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instr_is_32bit = 1'b1;
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instr_out = instr_in;
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invalid = 1'b0;
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end else begin
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instr_is_32bit = 1'b0;
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instr_out = 32'h0;
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invalid = 1'b0;
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casez (instr_in[15:0])
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16'h0: invalid = 1'b1;
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`RVOPC_C_ADDI4SPN: instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(rd_s) | rfmt_rs1(5'h2)
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| {2'h0, instr_in[10:7], instr_in[12:11], instr_in[5], instr_in[6], 2'b00, 20'h00000};
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`RVOPC_C_LW: instr_out = `RVOPC_NOZ_LW | rfmt_rd(rd_s) | rfmt_rs1(rs1_s)
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| {5'h00, instr_in[5], instr_in[12:10], instr_in[6], 2'b00, 20'h00000};
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`RVOPC_C_SW: instr_out = `RVOPC_NOZ_SW | rfmt_rs2(rs2_s) | rfmt_rs1(rs1_s)
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| {5'h00, instr_in[5], instr_in[12], 13'h000, instr_in[11:10], instr_in[6], 2'b00, 7'h00};
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`RVOPC_C_ADDI: instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(rd_l) | rfmt_rs1(rs1_l) | imm_ci;
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`RVOPC_C_JAL: instr_out = `RVOPC_NOZ_JAL | rfmt_rd(5'h1) | imm_cj;
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`RVOPC_C_J: instr_out = `RVOPC_NOZ_JAL | rfmt_rd(5'h0) | imm_cj;
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`RVOPC_C_LI: instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(rd_l) | imm_ci;
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`RVOPC_C_LUI: begin
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if (rd_l == 5'h2) begin
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// addi16sp
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instr_out = `RVOPC_NOZ_ADDI | rfmt_rd(5'h2) | rfmt_rs1(5'h2) |
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{{3{instr_in[12]}}, instr_in[4:3], instr_in[5], instr_in[2], instr_in[6], 24'h000000};
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end else begin
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instr_out = `RVOPC_NOZ_LUI | rfmt_rd(rd_l) | {{15{instr_in[12]}}, instr_in[6:2], 12'h000};
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end
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invalid = ~|{instr_in[12], instr_in[6:2]}; // RESERVED if imm == 0
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end
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`RVOPC_C_SLLI: instr_out = `RVOPC_NOZ_SLLI | rfmt_rd(rs1_l) | rfmt_rs1(rs1_l) | imm_ci;
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`RVOPC_C_SRAI: instr_out = `RVOPC_NOZ_SRAI | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | imm_ci;
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`RVOPC_C_SRLI: instr_out = `RVOPC_NOZ_SRLI | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | imm_ci;
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`RVOPC_C_ANDI: instr_out = `RVOPC_NOZ_ANDI | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | imm_ci;
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`RVOPC_C_AND: instr_out = `RVOPC_NOZ_AND | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s);
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`RVOPC_C_OR: instr_out = `RVOPC_NOZ_OR | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s);
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`RVOPC_C_XOR: instr_out = `RVOPC_NOZ_XOR | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s);
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`RVOPC_C_SUB: instr_out = `RVOPC_NOZ_SUB | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s);
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`RVOPC_C_ADD: begin
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if (|rs2_l) begin
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instr_out = `RVOPC_NOZ_ADD | rfmt_rd(rd_l) | rfmt_rs1(rs1_l) | rfmt_rs2(rs2_l);
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end else if (|rs1_l) begin // jalr
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instr_out = `RVOPC_NOZ_JALR | rfmt_rd(5'h1) | rfmt_rs1(rs1_l);
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end else begin // ebreak
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instr_out = `RVOPC_NOZ_EBREAK;
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end
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end
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`RVOPC_C_MV: begin
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if (|rs2_l) begin // mv
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instr_out = `RVOPC_NOZ_ADD | rfmt_rd(rd_l) | rfmt_rs2(rs2_l);
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end else begin // jr
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instr_out = `RVOPC_NOZ_JALR | rfmt_rs1(rs1_l);
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invalid = ~|rs1_l; // RESERVED
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end
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end
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`RVOPC_C_LWSP: begin
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instr_out = `RVOPC_NOZ_LW | rfmt_rd(rd_l) | rfmt_rs1(5'h2) |
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{4'h0, instr_in[3:2], instr_in[12], instr_in[6:4], 2'b00, 20'h00000};
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invalid = ~|rd_l; // RESERVED
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end
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`RVOPC_C_SWSP: instr_out = `RVOPC_NOZ_SW | rfmt_rs2(rs2_l) | rfmt_rs1(5'h2)
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| {4'h0, instr_in[8:7], instr_in[12], 13'h0000, instr_in[11:9], 2'b00, 7'h00};
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`RVOPC_C_BEQZ: instr_out = `RVOPC_NOZ_BEQ | rfmt_rs1(rs1_s) | imm_cb;
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`RVOPC_C_BNEZ: instr_out = `RVOPC_NOZ_BNE | rfmt_rs1(rs1_s) | imm_cb;
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// Optional Zbc instructions:
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`RVOPC_C_LBU: begin
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instr_out = `RVOPC_NOZ_LBU | rfmt_rd(rd_s) | rfmt_rs1(rs1_s) | imm_c_lb;
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invalid = ~|EXTENSION_ZCB;
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end
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`RVOPC_C_LHU: begin
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instr_out = `RVOPC_NOZ_LHU | rfmt_rd(rd_s) | rfmt_rs1(rs1_s) | imm_c_lh;
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invalid = ~|EXTENSION_ZCB;
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end
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`RVOPC_C_LH: begin
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instr_out = `RVOPC_NOZ_LH | rfmt_rd(rd_s) | rfmt_rs1(rs1_s) | imm_c_lh;
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invalid = ~|EXTENSION_ZCB;
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end
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`RVOPC_C_SB: begin
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instr_out = `RVOPC_NOZ_SB | rfmt_rd(rd_s) | rfmt_rs1(rs1_s) | imm_c_lb;
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invalid = ~|EXTENSION_ZCB;
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end
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`RVOPC_C_SH: begin
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instr_out = `RVOPC_NOZ_SH | rfmt_rd(rd_s) | rfmt_rs1(rs1_s) | imm_c_lh;
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invalid = ~|EXTENSION_ZCB;
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end
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`RVOPC_C_ZEXT_B: begin
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instr_out = `RVOPC_NOZ_ANDI | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | 32'h0ff00000;
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invalid = ~|EXTENSION_ZCB;
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end
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`RVOPC_C_SEXT_B: begin
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instr_out = `RVOPC_NOZ_SEXT_B | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s);
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invalid = ~|EXTENSION_ZCB || ~|EXTENSION_ZBB;
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end
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`RVOPC_C_ZEXT_H: begin
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instr_out = `RVOPC_NOZ_ZEXT_H | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s);
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invalid = ~|EXTENSION_ZCB || ~|EXTENSION_ZBB;
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end
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`RVOPC_C_SEXT_H: begin
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instr_out = `RVOPC_NOZ_SEXT_H | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s);
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invalid = ~|EXTENSION_ZCB || ~|EXTENSION_ZBB;
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end
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`RVOPC_C_NOT: begin
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instr_out = `RVOPC_NOZ_XORI | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | 32'hfff00000;
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invalid = ~|EXTENSION_ZCB;
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end
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`RVOPC_C_MUL: begin
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instr_out = `RVOPC_NOZ_MUL | rfmt_rd(rs1_s) | rfmt_rs1(rs1_s) | rfmt_rs2(rs2_s);
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invalid = ~|EXTENSION_ZCB || ~|EXTENSION_M;
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end
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default: invalid = 1'b1;
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endcase
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end
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end
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end
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endgenerate
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endmodule
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`ifndef YOSYS
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`default_nettype wire
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`endif
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