217 lines
4.5 KiB
ArmAsm
217 lines
4.5 KiB
ArmAsm
#include "hazard3_csr.h"
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#define IO_BASE 0x80000000
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#define IO_PRINT_CHAR (IO_BASE + 0x0)
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#define IO_PRINT_U32 (IO_BASE + 0x4)
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#define IO_EXIT (IO_BASE + 0x8)
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// Provide trap vector table, reset handler and weak default trap handlers for
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// Hazard3. This is not a crt0: the reset handler calls an external _start
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.option push
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.option norelax
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.section .vectors
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.macro VEC name:req
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.p2align 2
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j \name
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.p2align 2
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.endm
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// ----------------------------------------------------------------------------
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// Vector table (must be at least aligned to its size rounded up to power of 2)
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.p2align 12
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.vector_table:
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// Single exception vector, also takes IRQs if vectoring is disabled
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VEC handle_exception
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// Standard interrupts, if vectoring is enabled
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// Note: global EIRQ does not fire. Instead we have 16 separate vectors
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// handle_exception ^^^ takes the slot where U-mode softirq would be
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VEC .halt
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VEC .halt
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VEC isr_machine_softirq
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VEC .halt
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VEC .halt
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VEC .halt
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VEC isr_machine_timer
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VEC .halt
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VEC .halt
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VEC .halt
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VEC isr_external_irq
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VEC .halt
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VEC .halt
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VEC .halt
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VEC .halt
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// ----------------------------------------------------------------------------
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// Reset handler
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.reset_handler:
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// Set counters running, as they are off by default. This may trap if counters
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// are unimplemented, so catch the trap and continue.
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la a0, 1f
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csrw mtvec, a0
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csrci mcountinhibit, 0x5
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.p2align 2
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1:
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// Set up trap vector table. mtvec LSB enables vectoring
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la a0, .vector_table + 1
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csrw mtvec, a0
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// Put spare cores to sleep before setting up core 0 stack
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csrr a0, mhartid
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bnez a0, .core1_wait
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// Set up stack pointer before doing anything else
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la sp, __stack_top
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// newlib _start expects argc, argv on the stack. Leave stack 16-byte aligned.
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addi sp, sp, -16
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li a0, 1
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sw a0, (sp)
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la a0, progname
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sw a0, 4(sp)
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jal _start
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j .halt
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.core1_wait:
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// IRQs disabled, but soft IRQ unmasked -> soft IRQ will exit WFI.
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csrci mstatus, 0x8
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csrw mie, 0x8
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.core1_wait_loop:
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wfi
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la a0, core1_entry_vector
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lw a0, (a0)
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beqz a0, .core1_wait_loop
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la sp, __stack_top - 0x10000
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jalr a0
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.p2align 2
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.global core1_entry_vector
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core1_entry_vector:
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.word 0
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.global _exit
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_exit:
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li a1, IO_EXIT
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sw a0, (a1)
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.global _sbrk
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_sbrk:
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la a1, heap_ptr
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lw a2, (a1)
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add a0, a0, a2
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sw a0, (a1)
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mv a0, a2
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ret
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.p2align 2
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heap_ptr:
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.word _end
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.global .halt
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.halt:
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j .halt
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progname:
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.asciz "hazard3-testbench"
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// ----------------------------------------------------------------------------
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// Weak handler/ISR symbols
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// Routine to print out trap name, trap address, and some core registers
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// (x8..x15, ra, sp). The default handlers are all patched into this routine,
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// so the CPU will print some basic diagnostics on any unhandled trap
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// (assuming the processor is not internally completely broken)
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// argument in x28, return in x27, trashes x28...x30
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_tb_puts:
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li x29, IO_PRINT_CHAR
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1:
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lbu x30, (x28)
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addi x28, x28, 1
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beqz x30, 2f
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sw x30, (x29)
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j 1b
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2:
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jr x27
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.macro print_reg str reg
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la x28, \str
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jal x27, _tb_puts
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sw \reg, (x31)
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.endm
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_weak_handler_name_in_x31:
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la x28, _str_unhandled_trap
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jal x27, _tb_puts
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mv x28, x31
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jal x27, _tb_puts
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la x28, _str_at_mepc
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jal x27, _tb_puts
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li x31, IO_PRINT_U32
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csrr x28, mepc
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sw x28, (x31)
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csrr x26, mcause
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bltz x26, 1f
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print_reg _str_mcause x26
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1:
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print_reg _str_s0 s0
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print_reg _str_s1 s1
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print_reg _str_a0 a0
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print_reg _str_a1 a1
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print_reg _str_a2 a2
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print_reg _str_a3 a3
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print_reg _str_a4 a4
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print_reg _str_a5 a5
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print_reg _str_ra ra
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print_reg _str_sp sp
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li x31, IO_EXIT
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li x30, -1
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sw x30, (x31)
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// Should be unreachable:
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j .halt
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_str_unhandled_trap: .asciz "*** Unhandled trap ***\n"
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_str_at_mepc: .asciz " @ mepc = "
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_str_mcause: .asciz " mcause = "
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_str_s0: .asciz "s0: "
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_str_s1: .asciz "s1: "
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_str_a0: .asciz "a0: "
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_str_a1: .asciz "a1: "
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_str_a2: .asciz "a2: "
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_str_a3: .asciz "a3: "
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_str_a4: .asciz "a4: "
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_str_a5: .asciz "a5: "
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_str_ra: .asciz "ra: "
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_str_sp: .asciz "sp: "
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// Provide a default weak handler for each trap, which calls into the above
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// diagnostic routine with the trap name (a null-terminated string) in x31
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.macro weak_handler name:req
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.p2align 2
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.global \name
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.weak \name
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\name:
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la x31, _str_\name
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j _weak_handler_name_in_x31
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_str_\name:
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.asciz "\name"
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.endm
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weak_handler handle_exception
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weak_handler isr_machine_softirq
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weak_handler isr_machine_timer
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weak_handler isr_external_irq
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// You can relax now
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.option pop
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