Luke Wren 5aca1381ac Couple of fixups for rvpy which I forgot to commit at some point		2022-03-01 20:27:18 +00:00
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bitmanip-random	Fix sim cmdline in bitmanip-random tests	2021-12-11 13:13:21 +00:00
common	Add exclusives monitor to testbench	2021-12-17 17:03:35 +00:00
coremark	Fix remaining fallout from tb args change	2021-12-11 09:53:39 +00:00
dhrystone	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
embench	Fix remaining fallout from tb args change	2021-12-11 09:53:39 +00:00
hello_multicore	Add minimal multicore launch code	2021-12-17 01:24:11 +00:00
hellow	Add some instructions to Readme	2021-07-24 11:53:08 +01:00
riscv-compliance	Delete the AMO ALU. Save around 80 LCs vs original implementation, maybe enables some more savings.	2021-12-18 00:35:13 +00:00
riscv-tests	Consolidate openocd and bin-load testbenches	2021-12-11 09:46:38 +00:00
rvcpp	Organise test directory into formal and sim	2021-05-23 07:42:35 +01:00
rvpy	Couple of fixups for rvpy which I forgot to commit at some point	2022-03-01 20:27:18 +00:00
sw_testcases	Add minimal multicore launch code	2021-12-17 01:24:11 +00:00
tb_cxxrtl	Add exclusives monitor to testbench	2021-12-17 17:03:35 +00:00