Hazard3/test/sim
Luke Wren 5b31e26790 tb Makefile: use clang++-16 explicitly, because clang++-18 (now default on Ubuntu 24.04) has a >20x compile time regression 2024-05-27 11:06:50 +01:00
..
bitmanip-random Add support for testcase return code propagation to rvcpp. 2024-03-20 01:05:24 +00:00
common Limit multilib-gen-gen to more-useful ISA combinations 2023-11-30 05:32:39 +00:00
coremark Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH 2023-03-31 01:53:28 +01:00
dhrystone Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH 2023-03-31 01:53:28 +01:00
embench Update embench config and readme 2023-03-31 03:02:06 +01:00
hello_multicore Add minimal multicore launch code 2021-12-17 01:24:11 +00:00
hellow Restore SW Makefiles to use whatever riscv32-unknown-elf toolchain is in PATH 2023-03-31 01:53:28 +01:00
riscv-compliance Fix +x permission of riscv-compliance/clean_all script 2023-04-01 04:42:15 +01:00
riscv-tests Debug tests: workaround recent GCC requiring Zicsr set for CSR instructions 2024-05-12 13:33:14 +01:00
rvcpp Set misa.b when all of Zba, Zbb and Zbs are enabled. 2024-05-11 12:13:35 +01:00
rvpy Make rvpy IO output look exactly like tb_cxxrtl (bringing up embench) 2022-07-06 23:53:11 +01:00
sw_testcases Set misa.b when all of Zba, Zbb and Zbs are enabled. 2024-05-11 12:13:35 +01:00
tb_cxxrtl tb Makefile: use clang++-16 explicitly, because clang++-18 (now default on Ubuntu 24.04) has a >20x compile time regression 2024-05-27 11:06:50 +01:00