200 lines
6.6 KiB
Verilog
200 lines
6.6 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021-2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// APB-to-APB asynchronous bridge for connecting DTM to DM, in case DTM is in
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// a different clock domain (e.g. running directly from crystal to get a
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// fixed baud reference)
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//
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// Note this module depends on the hazard3_sync_1bit module (a flop-chain
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// synchroniser) which should be reimplemented for your FPGA/process.
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`ifndef HAZARD3_REG_KEEP_ATTRIBUTE
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`define HAZARD3_REG_KEEP_ATTRIBUTE (* keep = 1'b1 *)
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`endif
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`default_nettype none
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module hazard3_apb_async_bridge #(
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parameter W_ADDR = 8,
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parameter W_DATA = 32,
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parameter N_SYNC_STAGES = 2
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) (
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// Resets assumed to be synchronised externally
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input wire clk_src,
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input wire rst_n_src,
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input wire clk_dst,
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input wire rst_n_dst,
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// APB port from Transport Module
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input wire src_psel,
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input wire src_penable,
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input wire src_pwrite,
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input wire [W_ADDR-1:0] src_paddr,
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input wire [W_DATA-1:0] src_pwdata,
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output wire [W_DATA-1:0] src_prdata,
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output wire src_pready,
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output wire src_pslverr,
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// APB port to Debug Module
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output wire dst_psel,
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output wire dst_penable,
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output wire dst_pwrite,
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output wire [W_ADDR-1:0] dst_paddr,
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output wire [W_DATA-1:0] dst_pwdata,
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input wire [W_DATA-1:0] dst_prdata,
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input wire dst_pready,
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input wire dst_pslverr
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);
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// ----------------------------------------------------------------------------
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// Clock-crossing registers
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// We're using a modified req/ack handshake:
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//
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// - Initially both req and ack are low
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// - src asserts req high
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// - dst responds with ack high and begins transfer
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// - src deasserts req once it sees ack high
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// - dst deasserts ack once:
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// - transfer is complete *and*
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// - dst sees req deasserted
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// - Once src sees ack low, a new transfer can begin.
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//
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// A NRZI toggle handshake might be more appropriate, but can cause spurious
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// bus accesses when only one side of the link is reset.
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`HAZARD3_REG_KEEP_ATTRIBUTE reg src_req;
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wire dst_req;
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`HAZARD3_REG_KEEP_ATTRIBUTE reg dst_ack;
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wire src_ack;
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// Note the launch registers are not resettable. We maintain setup/hold on
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// launch-to-capture paths thanks to the req/ack handshake. A stray reset
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// could violate this.
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//
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// The req/ack logic itself can be reset safely because the receiving domain
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// is protected from metastability by a 2FF synchroniser.
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`HAZARD3_REG_KEEP_ATTRIBUTE reg [W_ADDR + W_DATA + 1 -1:0] src_paddr_pwdata_pwrite; // launch
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`HAZARD3_REG_KEEP_ATTRIBUTE reg [W_ADDR + W_DATA + 1 -1:0] dst_paddr_pwdata_pwrite; // capture
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`HAZARD3_REG_KEEP_ATTRIBUTE reg [W_DATA + 1 -1:0] dst_prdata_pslverr; // launch
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`HAZARD3_REG_KEEP_ATTRIBUTE reg [W_DATA + 1 -1:0] src_prdata_pslverr; // capture
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hazard3_sync_1bit #(
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.N_STAGES (N_SYNC_STAGES)
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) sync_req (
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.clk (clk_dst),
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.rst_n (rst_n_dst),
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.i (src_req),
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.o (dst_req)
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);
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hazard3_sync_1bit #(
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.N_STAGES (N_SYNC_STAGES)
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) sync_ack (
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.clk (clk_src),
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.rst_n (rst_n_src),
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.i (dst_ack),
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.o (src_ack)
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);
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// ----------------------------------------------------------------------------
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// src state machine
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reg src_waiting_for_downstream;
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reg src_pready_r;
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always @ (posedge clk_src or negedge rst_n_src) begin
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if (!rst_n_src) begin
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src_req <= 1'b0;
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src_waiting_for_downstream <= 1'b0;
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src_prdata_pslverr <= {W_DATA + 1{1'b0}};
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src_pready_r <= 1'b1;
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end else if (src_waiting_for_downstream) begin
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if (src_req && src_ack) begin
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// Request was acknowledged, so deassert.
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src_req <= 1'b0;
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end else if (!(src_req || src_ack)) begin
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// Downstream transfer has finished, data is valid.
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src_pready_r <= 1'b1;
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src_waiting_for_downstream <= 1'b0;
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// Note this assignment is cross-domain (but data has been stable
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// for duration of ack synchronisation delay):
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src_prdata_pslverr <= dst_prdata_pslverr;
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end
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end else begin
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// paddr, pwdata and pwrite are all valid during the setup phase, and
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// APB defines the setup phase to always last one cycle and proceed
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// to access phase. So, we can ignore penable, and pready is ignored.
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if (src_psel) begin
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src_pready_r <= 1'b0;
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src_req <= 1'b1;
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src_waiting_for_downstream <= 1'b1;
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end
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end
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end
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// Bus request launch register is not resettable
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always @ (posedge clk_src) begin
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if (src_psel && !src_waiting_for_downstream)
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src_paddr_pwdata_pwrite <= {src_paddr, src_pwdata, src_pwrite};
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end
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assign {src_prdata, src_pslverr} = src_prdata_pslverr;
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assign src_pready = src_pready_r;
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// ----------------------------------------------------------------------------
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// dst state machine
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wire dst_bus_finish = dst_penable && dst_pready;
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reg dst_psel_r;
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reg dst_penable_r;
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always @ (posedge clk_dst or negedge rst_n_dst) begin
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if (!rst_n_dst) begin
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dst_ack <= 1'b0;
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end else if (dst_req) begin
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dst_ack <= 1'b1;
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end else if (!dst_req && dst_ack && !dst_psel_r) begin
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dst_ack <= 1'b0;
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end
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end
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always @ (posedge clk_dst or negedge rst_n_dst) begin
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if (!rst_n_dst) begin
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dst_psel_r <= 1'b0;
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dst_penable_r <= 1'b0;
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end else if (dst_req && !dst_ack) begin
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dst_psel_r <= 1'b1;
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// Note this assignment is cross-domain. The src register has been
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// stable for the duration of the req sync delay.
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dst_paddr_pwdata_pwrite <= src_paddr_pwdata_pwrite;
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end else if (dst_psel_r && !dst_penable_r) begin
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dst_penable_r <= 1'b1;
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end else if (dst_bus_finish) begin
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dst_psel_r <= 1'b0;
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dst_penable_r <= 1'b0;
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end
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end
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// Bus response launch register is not resettable
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always @ (posedge clk_dst) begin
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if (dst_bus_finish)
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dst_prdata_pslverr <= {dst_prdata, dst_pslverr};
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end
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assign dst_psel = dst_psel_r;
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assign dst_penable = dst_penable_r;
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assign {dst_paddr, dst_pwdata, dst_pwrite} = dst_paddr_pwdata_pwrite;
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endmodule
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`ifndef YOSYS
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`default_nettype wire
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`endif
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