Luke Wren 624d39669d Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.		2022-08-29 19:20:09 +01:00
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bus_compliance_1port	Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.	2022-08-29 19:20:09 +01:00
bus_compliance_2port	Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.	2022-08-29 19:20:09 +01:00
common	Add SBA patch-through to 1-core wrapper.	2022-07-03 15:17:44 +01:00
frontend_fetch_match	First pass at adding branch prediction	2022-06-15 02:05:46 +01:00
instruction_fetch_match	Fix up new asserts in hazard3_power_ctrl. Add power signals to formal TBs.	2022-08-29 19:20:09 +01:00
riscv-formal	Fix two frontend bugs: possibility for fetch to be blocked at CIR whilst also not going to FIFO (fixed by making those signals the complement of each other) and typo in the shift value for shifting into a CIR with 32 bits of contents, which is only reachable via a CIR-locked branch to an unaligned address.	2022-06-13 01:23:32 +01:00
.gitignore	Add simple formal bus properties check	2021-05-30 10:19:42 +01:00