90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
#ifndef _HAZARD3_IRQ_H
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#define _HAZARD3_IRQ_H
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#include "hazard3_csr.h"
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#include "stdint.h"
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#include "stdbool.h"
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// Should match processor configuration in testbench:
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#define NUM_IRQS 32
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#define MAX_PRIORITY 15
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// Declarations for irq_dispatch.S
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extern uintptr_t _external_irq_table[NUM_IRQS];
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extern uint32_t _external_irq_entry_count;
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#define h3irq_array_read(csr, index) (read_set_csr(csr, (index)) >> 16)
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#define h3irq_array_write(csr, index, data) (write_csr(csr, (index) | ((uint32_t)(data) << 16)))
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#define h3irq_array_set(csr, index, data) (set_csr(csr, (index) | ((uint32_t)(data) << 16)))
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#define h3irq_array_clear(csr, index, data) (clear_csr(csr, (index) | ((uint32_t)(data) << 16)))
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static inline void h3irq_enable(unsigned int irq, bool enable) {
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if (enable) {
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h3irq_array_set(hazard3_csr_meiea, irq >> 4, 1u << (irq & 0xfu));
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}
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else {
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h3irq_array_clear(hazard3_csr_meiea, irq >> 4, 1u << (irq & 0xfu));
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}
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}
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static inline bool h3irq_pending(unsigned int irq) {
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return h3irq_array_read(hazard3_csr_meipa, irq >> 4) & (1u << (irq & 0xfu));
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}
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static inline void h3irq_force_pending(unsigned int irq, bool force) {
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if (force) {
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h3irq_array_set(hazard3_csr_meifa, irq >> 4, 1u << (irq & 0xfu));
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}
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else {
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h3irq_array_clear(hazard3_csr_meifa, irq >> 4, 1u << (irq & 0xfu));
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}
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}
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static inline bool h3irq_is_forced(unsigned int irq) {
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return h3irq_array_read(hazard3_csr_meifa, irq >> 4) & (1u << (irq & 0xfu));
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}
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// -1 for no IRQ
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static inline int h3irq_get_current_irq() {
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uint32_t meicontext = read_csr(hazard3_csr_meicontext);
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return meicontext & 0x8000u ? -1 : (meicontext >> 4) & 0x1ffu;
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}
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static inline void h3irq_set_priority(unsigned int irq, uint32_t priority) {
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// Don't want read-modify-write, but no instruction for atomically writing
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// a bitfield. So, first drop priority to minimum, then set to the target
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// value. It should be safe to drop an IRQ's priority below its current
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// even from within that IRQ (but it is never safe to boost an IRQ when
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// it may already be in an older stack frame)
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h3irq_array_clear(hazard3_csr_meipra, irq >> 2, 0xfu << (4 * (irq & 0x3)));
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h3irq_array_set(hazard3_csr_meipra, irq >> 2, (priority & 0xfu) << (4 * (irq & 0x3)));
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}
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static inline void h3irq_set_handler(unsigned int irq, void (*handler)(void)) {
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_external_irq_table[irq] = (uintptr_t)handler;
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}
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static inline void global_irq_enable(bool en) {
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// mstatus.mie
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if (en) {
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set_csr(mstatus, 0x8);
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}
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else {
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clear_csr(mstatus, 0x8);
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}
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}
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static inline void external_irq_enable(bool en) {
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// mie.meie
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if (en) {
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set_csr(mie, 0x800);
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}
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else {
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clear_csr(mie, 0x800);
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}
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}
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#endif
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