73 lines
2.4 KiB
Verilog
73 lines
2.4 KiB
Verilog
/**********************************************************************
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* DO WHAT THE FUCK YOU WANT TO AND DON'T BLAME US PUBLIC LICENSE *
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* Version 3, April 2008 *
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* *
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* Copyright (C) 2018 Luke Wren *
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* *
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* Everyone is permitted to copy and distribute verbatim or modified *
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* copies of this license document and accompanying software, and *
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* changing either is allowed. *
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* *
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* TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION *
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* *
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* 0. You just DO WHAT THE FUCK YOU WANT TO. *
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* 1. We're NOT RESPONSIBLE WHEN IT DOESN'T FUCKING WORK. *
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* *
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*********************************************************************/
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module hazard5_shift_1bit_seq #(
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parameter W_DATA = 32,
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parameter W_SHAMT = 5
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) (
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input wire clk,
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input wire rst_n,
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input wire [W_DATA-1:0] din,
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input wire din_vld, // can be asserted at any time, we always respond
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input wire [W_SHAMT-1:0] shamt,
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input wire right_nleft,
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input wire arith,
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output wire [W_DATA-1:0] dout,
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output wire dout_vld,
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);
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reg [W_DATA-1:0] accum;
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reg [W_DATA-1:0] accum_next;
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reg [W_SHAMT-1:0] shamt_remaining;
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reg flipped;
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// Handle actual shifting
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wire sext = arith && accum[W_DATA - 1];
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always @ (*) begin: shift_unit
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accum_next = accum;
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if (din_vld) begin
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accum_next = din;
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end else if (shamt_remaining) begin
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if (right_nleft)
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accum_next = {sext, accum[W_DATA-1:1]};
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else
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accum_next = {accum << 1};
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end
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end
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// No reset on datapath
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always @ (posedge clk)
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accum <= accum_next;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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shamt_remaining <= {W_SHAMT{1'b0}};
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end else if (din_vld) begin
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shamt_remaining <= shamt;
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end else begin
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shamt_remaining <= shamt_remaining - |shamt_remaining;
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end
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end
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assign dout_vld = shamt_remaining == 0;
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assign dout = accum;
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endmodule
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